CLZ

Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010110(1)(1)(1)(1)Rd(1)(1)(1)(1)0001Rm
cond

A1

CLZ{<c>}{<q>} <Rd>, <Rm>

d = UInt(Rd); m = UInt(Rm); if d == 15 || m == 15 then UNPREDICTABLE;

T1

15141312111098765432101514131211109876543210
111110101011Rn1111Rd1000Rm

T1

CLZ{<c>}{<q>} <Rd>, <Rm>

d = UInt(Rd); m = UInt(Rm); n = UInt(Rn); if m != n || d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

CONSTRAINED UNPREDICTABLE behavior

If m != n, then one of the following behaviors must occur:

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>

For encoding A1: is the general-purpose source register, encoded in the "Rm" field.

For encoding T1: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); result = CountLeadingZeroBits(R[m]); R[d] = result<31:0>;

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:


Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

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