Error Synchronization Barrier is an error synchronization event that might also update DISR and VDISR. This instruction can be used at all Exception levels and in Debug state.
In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels. See Error Synchronization Barrier in the ARM(R) Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for Armv8-A architecture profile.
If the RAS Extension is not implemented, this instruction executes as a NOP.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | (1) | (1) | (1) | (1) | (0) | (0) | (0) | (0) | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |||
| cond | |||||||||||||||||||||||||||||||
if !HaveRASExt() then EndOfInstruction(); // Instruction executes as NOP if cond != '1110' then UNPREDICTABLE; // ESB must be encoded with AL condition
If cond != '1110', then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | (1) | (1) | (1) | (1) | 1 | 0 | (0) | 0 | (0) | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
if !HaveRASExt() then EndOfInstruction(); // Instruction executes as NOP if InITBlock() then UNPREDICTABLE;
If InITBlock(), then one of the following behaviors must occur:
if ConditionPassed() then EncodingSpecificOperations(); SynchronizeErrors(); AArch32.ESBOperation(); if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then AArch32.vESBOperation(); TakeUnmaskedSErrorInterrupts();
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.