Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses.
The T32 form of LDR (register) does not support register writeback.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 1 | 1 | P | U | 0 | W | 1 | Rn | Rt | imm5 | stype | 0 | Rm | |||||||||||||||||
| cond | |||||||||||||||||||||||||||||||
if P == '0' && W == '1' then SEE "LDRT"; t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1'); (shift_t, shift_n) = DecodeImmShift(stype, imm5); if m == 15 then UNPREDICTABLE; if wback && (n == 15 || n == t) then UNPREDICTABLE;
If wback && n == t, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 0 | Rm | Rn | Rt | ||||||
t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); (shift_t, shift_n) = (SRType_LSL, 0);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | != 1111 | Rt | 0 | 0 | 0 | 0 | 0 | 0 | imm2 | Rm | ||||||||||
| Rn | |||||||||||||||||||||||||||||||
if Rn == '1111' then SEE "LDR (literal)"; t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rt> |
For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used. If the PC is used, the instruction branches to the address (data) loaded to the PC. This branch is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. |
|
For encoding T1: is the general-purpose register to be transferred, encoded in the "Rt" field. | |
|
For encoding T2: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC can be used, provided the instruction is either outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches to the address (data) loaded to the PC. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. |
| +/- |
Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and
encoded in
|
| + |
Specifies the index register is added to the base register. |
| <Rm> |
Is the general-purpose index register, encoded in the "Rm" field. |
| <shift> |
The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts applied to a register. |
| <imm> |
If present, the size of the left shift to apply to the value from <Rm>, in the range 1-3. <imm> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as 0b00. |
if CurrentInstrSet() == InstrSet_A32 then if ConditionPassed() then EncodingSpecificOperations(); offset = Shift(R[m], shift_t, shift_n, PSTATE.C); offset_addr = if add then (R[n] + offset) else (R[n] - offset); address = if index then offset_addr else R[n]; data = MemU[address,4]; if wback then R[n] = offset_addr; if t == 15 then if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; else R[t] = data; else if ConditionPassed() then EncodingSpecificOperations(); offset = Shift(R[m], shift_t, shift_n, PSTATE.C); offset_addr = (R[n] + offset); address = offset_addr; data = MemU[address,4]; if t == 15 then if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE; else R[t] = data;
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.