Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses.
The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is actually running in User mode.
LDRSHT is unpredictable in Hyp mode.
The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged.
The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 0 | U | 1 | 1 | 1 | Rn | Rt | imm4H | 1 | 1 | 1 | 1 | imm4L | |||||||||||||||
| cond | |||||||||||||||||||||||||||||||
t = UInt(Rt); n = UInt(Rn); postindex = TRUE; add = (U == '1'); register_form = FALSE; imm32 = ZeroExtend(imm4H:imm4L, 32); integer m = integer UNKNOWN; if t == 15 || n == 15 || n == t then UNPREDICTABLE;
If n == 15, then one of the following behaviors must occur:
If n == t && n != 15, then one of the following behaviors must occur:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 0 | U | 0 | 1 | 1 | Rn | Rt | (0) | (0) | (0) | (0) | 1 | 1 | 1 | 1 | Rm | ||||||||||||
| cond | |||||||||||||||||||||||||||||||
t = UInt(Rt); n = UInt(Rn); m = UInt(Rm); postindex = TRUE; add = (U == '1'); register_form = TRUE; bits(32) imm32 = bits(32) UNKNOWN; if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;
If n == t && n != 15, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | != 1111 | Rt | 1 | 1 | 1 | 0 | imm8 | |||||||||||||
| Rn | |||||||||||||||||||||||||||||||
if Rn == '1111' then SEE "LDRSH (literal)"; t = UInt(Rt); n = UInt(Rn); postindex = FALSE; add = TRUE; register_form = FALSE; imm32 = ZeroExtend(imm8, 32); integer m = integer UNKNOWN; if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rt> |
Is the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. |
| <Rm> |
Is the general-purpose index register, encoded in the "Rm" field. |
| + |
Specifies the offset is added to the base register. |
| <imm> |
For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field. |
|
For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field. |
if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then UNPREDICTABLE; // Hyp mode offset = if register_form then R[m] else imm32; offset_addr = if add then (R[n] + offset) else (R[n] - offset); address = if postindex then R[n] else offset_addr; data = MemU_unpriv[address,2]; if postindex then R[n] = offset_addr; R[t] = SignExtend(data, 32);
If PSTATE.EL == EL2, then one of the following behaviors must occur:
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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