MOV, MOVS (register) -- AArch32

If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 and T3 ) .

d = UInt(Rd); m = UInt(Rm); setflags = (S == '1'); (shift_t, shift_n) = DecodeImmShift(stype, imm5);

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	1	0	D	Rm	Rd

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	!= 11	imm5	Rm	Rd
	op

d = UInt(Rd); m = UInt(Rm); setflags = !InITBlock(); (shift_t, shift_n) = DecodeImmShift(op, imm5); if op == '00' && imm5 == '00000' && InITBlock() then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If op == '00' && imm5 == '00000' && InITBlock(), then one of the following behaviors must occur:

d = UInt(Rd); m = UInt(Rm); setflags = (S == '1'); (shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2); if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

Assembler Symbols

Alias Conditions

Alias	Of variant	Is preferred when
ASRS (immediate)	T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value)	S == '1' && stype == '10'
ASRS (immediate)	T2	op == '10' && !InITBlock()
ASR (immediate)	T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value)	S == '0' && stype == '10'
ASR (immediate)	T2	op == '10' && InITBlock()
LSLS (immediate)	T3 (MOVS, shift or rotate by value)	S == '1' && imm3:Rd:imm2 != '000xxxx00' && stype == '00'
LSLS (immediate)	A1 (MOVS, shift or rotate by value)	S == '1' && imm5 != '00000' && stype == '00'
LSLS (immediate)	T2	op == '00' && imm5 != '00000' && !InITBlock()
LSL (immediate)	T3 (MOV, shift or rotate by value)	S == '0' && imm3:Rd:imm2 != '000xxxx00' && stype == '00'
LSL (immediate)	A1 (MOV, shift or rotate by value)	S == '0' && imm5 != '00000' && stype == '00'
LSL (immediate)	T2	op == '00' && imm5 != '00000' && InITBlock()
LSRS (immediate)	T3 (MOVS, shift or rotate by value), A1 (MOVS, shift or rotate by value)	S == '1' && stype == '01'
LSRS (immediate)	T2	op == '01' && !InITBlock()
LSR (immediate)	T3 (MOV, shift or rotate by value), A1 (MOV, shift or rotate by value)	S == '0' && stype == '01'
LSR (immediate)	T2	op == '01' && InITBlock()
RORS (immediate)	T3 (MOVS, shift or rotate by value)	S == '1' && imm3:Rd:imm2 != '000xxxx00' && stype == '11'
RORS (immediate)	A1 (MOVS, shift or rotate by value)	S == '1' && imm5 != '00000' && stype == '11'
ROR (immediate)	T3 (MOV, shift or rotate by value)	S == '0' && imm3:Rd:imm2 != '000xxxx00' && stype == '11'
ROR (immediate)	A1 (MOV, shift or rotate by value)	S == '0' && imm5 != '00000' && stype == '11'
RRXS	T3 (MOVS, rotate right with extend)	S == '1' && imm3 == '000' && imm2 == '00' && stype == '11'
RRXS	A1 (MOVS, rotate right with extend)	S == '1' && imm5 == '00000' && stype == '11'
RRX	T3 (MOV, rotate right with extend)	S == '0' && imm3 == '000' && imm2 == '00' && stype == '11'
RRX	A1 (MOV, rotate right with extend)	S == '0' && imm5 == '00000' && stype == '11'

Operation

if ConditionPassed() then EncodingSpecificOperations(); (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C); result = shifted; if d == 15 then if setflags then ALUExceptionReturn(result); else ALUWritePC(result); else R[d] = result; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged

Operational information

If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:

The execution time of this instruction is independent of:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
- The values of the data supplied in any of its registers.
- The values of the NZCV flags.

Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	1	1	0	1	S	(0)	(0)	(0)	(0)	Rd				imm5					stype		0	Rm
cond

<Rd>	For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used: For the MOV variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. Arm deprecates use of the instruction if <Rn> is the PC. For the MOVS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>. Arm deprecates use of the instruction if <Rn> is not the LR, or if the optional shift or RRX argument is specified.
	For encoding T1: is the general-purpose destination register, encoded in the "D:Rd" field. If the PC is used: The instruction causes a branch to the address moved to the PC. This is a simple branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. The instruction must either be outside an IT block or the last instruction of an IT block.
	For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.

<amount>	For encoding A1: is the shift amount, in the range 0 to 31 (when <shift> = LSL), or 1 to 31 (when <shift> = ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm5" field as <amount> modulo 32.
	For encoding T2: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm5" field as <amount> modulo 32.
	For encoding T3: is the shift amount, in the range 0 to 31 (when <shift> = LSL) or 1 to 31 (when <shift> = ROR), or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.