Move (register-shifted register) copies a register-shifted register value to the destination register. It can optionally update the condition flags based on the value.
This instruction is used by the aliases ASRS (register), ASR (register), LSLS (register), LSL (register), LSRS (register), LSR (register), RORS (register), and ROR (register).
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | S | (0) | (0) | (0) | (0) | Rd | Rs | 0 | stype | 1 | Rm | |||||||||||||
| cond | |||||||||||||||||||||||||||||||
d = UInt(Rd); m = UInt(Rm); s = UInt(Rs); setflags = (S == '1'); shift_t = DecodeRegShift(stype); if d == 15 || m == 15 || s == 15 then UNPREDICTABLE;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | x | x | x | Rs | Rdm | ||||
| op | |||||||||||||||
if !(op IN {'0010', '0011', '0100', '0111'}) then SEE "Related encodings"; d = UInt(Rdm); m = UInt(Rdm); s = UInt(Rs); setflags = !InITBlock(); shift_t = DecodeRegShift(op<2>:op<0>);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | stype | S | Rm | 1 | 1 | 1 | 1 | Rd | 0 | 0 | 0 | 0 | Rs | ||||||||||
MOVS.W <Rd>, <Rm>, <shift> <Rs> // (Outside IT block, and <Rd>, <Rm>, <shift>, <Rs> can be represented in T1)
MOV<c>.W <Rd>, <Rm>, <shift> <Rs> // (Inside IT block, and <Rd>, <Rm>, <shift>, <Rs> can be represented in T1)
d = UInt(Rd); m = UInt(Rm); s = UInt(Rs); setflags = (S == '1'); shift_t = DecodeRegShift(stype); if d == 15 || m == 15 || s == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
Related encodings: In encoding T1, for an op field value that is not described above, see Data-processing (two low registers).
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <Rdm> |
Is the general-purpose source register and the destination register, encoded in the "Rdm" field. |
| <Rd> |
Is the general-purpose destination register, encoded in the "Rd" field. |
| <Rm> |
Is the general-purpose source register, encoded in the "Rm" field. |
| <shift> |
Is the type of shift to be applied to the second source register,
encoded in
|
| <Rs> |
Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field. |
| Alias | Of variant | Is preferred when |
|---|---|---|
| ASRS (register) | A1 (flag setting) | S == '1' && stype == '10' |
| ASRS (register) | T1 (arithmetic shift right) | op == '0100' && !InITBlock() |
| ASRS (register) | T2 (flag setting) | stype == '10' && S == '1' |
| ASR (register) | A1 (not flag setting) | S == '0' && stype == '10' |
| ASR (register) | T1 (arithmetic shift right) | op == '0100' && InITBlock() |
| ASR (register) | T2 (not flag setting) | stype == '10' && S == '0' |
| LSLS (register) | A1 (flag setting) | S == '1' && stype == '00' |
| LSLS (register) | T1 (logical shift left) | op == '0010' && !InITBlock() |
| LSLS (register) | T2 (flag setting) | stype == '00' && S == '1' |
| LSL (register) | A1 (not flag setting) | S == '0' && stype == '00' |
| LSL (register) | T1 (logical shift left) | op == '0010' && InITBlock() |
| LSL (register) | T2 (not flag setting) | stype == '00' && S == '0' |
| LSRS (register) | A1 (flag setting) | S == '1' && stype == '01' |
| LSRS (register) | T1 (logical shift right) | op == '0011' && !InITBlock() |
| LSRS (register) | T2 (flag setting) | stype == '01' && S == '1' |
| LSR (register) | A1 (not flag setting) | S == '0' && stype == '01' |
| LSR (register) | T1 (logical shift right) | op == '0011' && InITBlock() |
| LSR (register) | T2 (not flag setting) | stype == '01' && S == '0' |
| RORS (register) | A1 (flag setting) | S == '1' && stype == '11' |
| RORS (register) | T1 (rotate right) | op == '0111' && !InITBlock() |
| RORS (register) | T2 (flag setting) | stype == '11' && S == '1' |
| ROR (register) | A1 (not flag setting) | S == '0' && stype == '11' |
| ROR (register) | T1 (rotate right) | op == '0111' && InITBlock() |
| ROR (register) | T2 (not flag setting) | stype == '11' && S == '0' |
if ConditionPassed() then EncodingSpecificOperations(); shift_n = UInt(R[s]<7:0>); (result, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C); R[d] = result; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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