PLD, PLDW (register) -- AArch32

PLD, PLDW (register)

Preload Data (register) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.

The PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write.

The effect of a PLD or PLDW instruction is implementation defined. For more information, see Preloading caches.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	1	1	1	U	R	0	1	Rn				(1)	(1)	(1)	(1)	imm5					stype		0	Rm

Preload read, optional shift or rotate (R == 1 && !(imm5 == 00000 && stype == 11))

PLD{<c>}{<q>} [<Rn>, {+/-}<Rm> {, <shift> #<amount>}]

Preload read, rotate right with extend (R == 1 && imm5 == 00000 && stype == 11)

PLD{<c>}{<q>} [<Rn>, {+/-}<Rm> , RRX]

Preload write, optional shift or rotate (R == 0 && !(imm5 == 00000 && stype == 11))

PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> {, <shift> #<amount>}]

Preload write, rotate right with extend (R == 0 && imm5 == 00000 && stype == 11)

PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> , RRX]

n = UInt(Rn); m = UInt(Rm); add = (U == '1'); is_pldw = (R == '0'); (shift_t, shift_n) = DecodeImmShift(stype, imm5); if m == 15 || (n == 15 && is_pldw) then UNPREDICTABLE;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	0	0	0	0	W	1	!= 1111				1	1	1	1	0	0	0	0	0	0	imm2		Rm
												Rn

Preload read (W == 0)

PLD{<c>}{<q>} [<Rn>, {+}<Rm> {, LSL #<amount>}]

Preload write (W == 1)

PLDW{<c>}{<q>} [<Rn>, {+}<Rm> {, LSL #<amount>}]

if Rn == '1111' then SEE "PLD (literal)"; n = UInt(Rn); m = UInt(Rm); add = TRUE; is_pldw = (W == '1'); (shift_t, shift_n) = (SRType_LSL, UInt(imm2)); if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	For encoding A1: see Standard assembler syntax fields. <c> must be AL or omitted.
	For encoding T1: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rn>	For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used.
	For encoding T1: is the general-purpose base register, encoded in the "Rn" field.

+/-

Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:

U	+/-
0	-
1	+

+	Specifies the index register is added to the base register.

<Rm>	Is the general-purpose index register, encoded in the "Rm" field.

<shift>

Is the type of shift to be applied to the index register, encoded in stype:

stype	<shift>
00	LSL
01	LSR
10	ASR
11	ROR

<amount>	For encoding A1: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.
	For encoding T1: is the shift amount, in the range 0 to 3, defaulting to 0 and encoded in the "imm2" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); offset = Shift(R[m], shift_t, shift_n, PSTATE.C); address = if add then (R[n] + offset) else (R[n] - offset); if is_pldw then Hint_PreloadDataForWrite(address); else Hint_PreloadData(address);

Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06