SHA256SU0

SHA256 schedule update 0.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_SHA256)

313029282726252423222120191817161514131211109876543210
111100111D11size10Vd001111M0Vm

A1

SHA256SU0.32 <Qd>, <Qm>

if !HaveSHA256Ext() then UNDEFINED; if size != '10' then UNDEFINED; if Vd<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); m = UInt(M:Vm);

T1
(FEAT_SHA256)

15141312111098765432101514131211109876543210
111111111D11size10Vd001111M0Vm

T1

SHA256SU0.32 <Qd>, <Qm>

if InITBlock() then UNPREDICTABLE; if !HaveSHA256Ext() then UNDEFINED; if size != '10' then UNDEFINED; if Vd<0> == '1' || Vm<0> == '1' then UNDEFINED; d = UInt(D:Vd); m = UInt(M:Vm);

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

Operation

if ConditionPassed() then bits(128) result; EncodingSpecificOperations(); CheckCryptoEnabled32(); x = Q[d>>1]; y = Q[m>>1]; t = y<31:0> : x<127:32>; for e = 0 to 3 elt = Elem[t, e, 32]; elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3); Elem[result, e, 32] = elt + Elem[x, e, 32]; Q[d>>1] = result;

Operational information

If CPSR.DIT is 1:


Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

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