STC -- AArch32

STC

Store data to System register calculates an address from a base register value and an immediate offset, and stores a word from the DBGDTRRXint System register to memory. It can use offset, post-indexed, pre-indexed, or unindexed addressing. For information about memory accesses, see Memory accesses.

In an implementation that includes EL2, the permitted STC access to DBGDTRRXint can be trapped to Hyp mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general Non-secure System register accesses to debug registers.

For simplicity, the STC pseudocode does not show this possible trap to Hyp mode.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	1	0	P	U	0	W	0	Rn				0	1	0	1	1	1	1	0	imm8
cond

if P == '0' && U == '0' && W == '0' then UNDEFINED; n = UInt(Rn); cp = 14; imm32 = ZeroExtend(imm8:'00', 32); index = (P == '1'); add = (U == '1'); wback = (W == '1'); if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

If n == 15 && wback, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction executes without writeback of the base address.
The instruction executes with writeback to the PC. The instruction is handled as described in Using R15.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	1	0	P	U	0	W	0	Rn				0	1	0	1	1	1	1	0	imm8

Offset (P == 1 && W == 0)

STC{<c>}{<q>} p14, c5, [<Rn>{, #{+/-}<imm>}]

Post-indexed (P == 0 && W == 1)

STC{<c>}{<q>} p14, c5, [<Rn>], #{+/-}<imm>

Pre-indexed (P == 1 && W == 1)

STC{<c>}{<q>} p14, c5, [<Rn>, #{+/-}<imm>]!

Unindexed (P == 0 && U == 1 && W == 0)

STC{<c>}{<q>} p14, c5, [<Rn>], <option>

CONSTRAINED UNPREDICTABLE behavior

If n == 15, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction executes without writeback of the base address.
The instruction executes with writeback to the PC. The instruction is handled as described in Using R15.

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rn>	For the offset or unindexed variant: is the general-purpose base register, encoded in the "Rn" field. The PC can be used, but this is deprecated.
	For the offset, post-indexed or pre-indexed variant: is the general-purpose base register, encoded in the "Rn" field.

Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction.

+/-

Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and encoded in U:

U	+/-
0	-
1	+

<imm>

Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as <imm>/4.

Operation

if ConditionPassed() then EncodingSpecificOperations(); offset_addr = if add then (R[n] + imm32) else (R[n] - imm32); address = if index then offset_addr else R[n]; // System register read from DBGDTRRXint. AArch32.SysRegRead(cp, ThisInstr(), address<31:0>); if wback then R[n] = offset_addr;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06