SXTB16

Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 1111011010001111Rdrotate(0)(0)0111Rm
cond

A1

SXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}

d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); if d == 15 || m == 15 then UNPREDICTABLE;

T1

15141312111098765432101514131211109876543210
11111010001011111111Rd1(0)rotateRm

T1

SXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}

d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000'); if d == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>

Is the general-purpose source register, encoded in the "Rm" field.

<amount>

Is the rotate amount, encoded in rotate:

rotate <amount>
00 (omitted)
01 8
10 16
11 24

Operation

if ConditionPassed() then EncodingSpecificOperations(); rotated = ROR(R[m], rotation); R[d]<15:0> = SignExtend(rotated<7:0>, 16); R[d]<31:16> = SignExtend(rotated<23:16>, 16);

Operational information

If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:


Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

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