Test Equivalence (register) performs a bitwise exclusive-OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | Rn | (0) | (0) | (0) | (0) | imm5 | stype | 0 | Rm | ||||||||||||||
| cond | |||||||||||||||||||||||||||||||
n = UInt(Rn); m = UInt(Rm); (shift_t, shift_n) = DecodeImmShift(stype, imm5);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | Rn | (0) | imm3 | 1 | 1 | 1 | 1 | imm2 | stype | Rm | ||||||||||
n = UInt(Rn); m = UInt(Rm); (shift_t, shift_n) = DecodeImmShift(stype, imm3:imm2); if n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.
| <c> |
| <q> |
| <shift> |
Is the type of shift to be applied to the second source register,
encoded in
|
if ConditionPassed() then EncodingSpecificOperations(); (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C); result = R[n] EOR shifted; PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged
If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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