VCMLA (by element)

Vector Complex Multiply Accumulate (by element).

This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on complex numbers from the first source register and the destination register with the specified complex number from the second source register:

The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_FCMA)

313029282726252423222120191817161514131211109876543210
11111110SDrotVnVd1000NQM0Vm

64-bit SIMD vector of half-precision floating-point (S == 0 && Q == 0)

VCMLA{<q>}.F16 <Dd>, <Dn>, <Dm>[<index>], #<rotate>

64-bit SIMD vector of single-precision floating-point (S == 1 && Q == 0)

VCMLA{<q>}.F32 <Dd>, <Dn>, <Dm>[0], #<rotate>

128-bit SIMD vector of half-precision floating-point (S == 0 && Q == 1)

VCMLA{<q>}.F16 <Qd>, <Qn>, <Dm>[<index>], #<rotate>

128-bit SIMD vector of single-precision floating-point (S == 1 && Q == 1)

VCMLA{<q>}.F32 <Qd>, <Qn>, <Dm>[0], #<rotate>

if !HaveFCADDExt() then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED; d = UInt(D:Vd); n = UInt(N:Vn); m = if S=='1' then UInt(M:Vm) else UInt(Vm); esize = 16 << UInt(S); if !HaveFP16Ext() && esize == 16 then UNDEFINED; elements = 64 DIV esize; regs = if Q == '0' then 1 else 2; index = if S=='1' then 0 else UInt(M);

T1
(FEAT_FCMA)

15141312111098765432101514131211109876543210
11111110SDrotVnVd1000NQM0Vm

64-bit SIMD vector of half-precision floating-point (S == 0 && Q == 0)

VCMLA{<q>}.F16 <Dd>, <Dn>, <Dm>[<index>], #<rotate>

64-bit SIMD vector of single-precision floating-point (S == 1 && Q == 0)

VCMLA{<q>}.F32 <Dd>, <Dn>, <Dm>[0], #<rotate>

128-bit SIMD vector of half-precision floating-point (S == 0 && Q == 1)

VCMLA{<q>}.F16 <Qd>, <Qn>, <Dm>[<index>], #<rotate>

128-bit SIMD vector of single-precision floating-point (S == 1 && Q == 1)

VCMLA{<q>}.F32 <Qd>, <Qn>, <Dm>[0], #<rotate>

if InITBlock() then UNPREDICTABLE; if !HaveFCADDExt() then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED; d = UInt(D:Vd); n = UInt(N:Vn); m = if S=='1' then UInt(M:Vm) else UInt(Vm); esize = 16 << UInt(S); if !HaveFP16Ext() && esize == 16 then UNDEFINED; elements = 64 DIV esize; regs = if Q == '0' then 1 else 2; index = if S=='1' then 0 else UInt(M);

Assembler Symbols

<q>

See Standard assembler syntax fields.

<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qn>

Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>

For the half-precision scalar variant: is the 64-bit name of the second SIMD&FP source register, encoded in the "Vm" field.

For the single-precision scalar variant: is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<index>

Is the element index in the range 0 to 1, encoded in the "M" field.

<rotate>

Is the rotation to be applied to elements in the second SIMD&FP source register, encoded in rot:

rot <rotate>
00 0
01 90
10 180
11 270

Operation

EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for r = 0 to regs-1 operand1 = D[n+r]; operand2 = Din[m]; operand3 = D[d+r]; for e = 0 to (elements DIV 2)-1 bits(esize) element1; bits(esize) element2; bits(esize) element3; bits(esize) element4; case rot of when '00' element1 = Elem[operand2,index*2,esize]; element2 = Elem[operand1,e*2,esize]; element3 = Elem[operand2,index*2+1,esize]; element4 = Elem[operand1,e*2,esize]; when '01' element1 = FPNeg(Elem[operand2,index*2+1,esize]); element2 = Elem[operand1,e*2+1,esize]; element3 = Elem[operand2,index*2,esize]; element4 = Elem[operand1,e*2+1,esize]; when '10' element1 = FPNeg(Elem[operand2,index*2,esize]); element2 = Elem[operand1,e*2,esize]; element3 = FPNeg(Elem[operand2,index*2+1,esize]); element4 = Elem[operand1,e*2,esize]; when '11' element1 = Elem[operand2,index*2+1,esize]; element2 = Elem[operand1,e*2+1,esize]; element3 = FPNeg(Elem[operand2,index*2,esize]); element4 = Elem[operand1,e*2+1,esize]; result1 = FPMulAdd(Elem[operand3,e*2,esize],element2,element1, StandardFPSCRValue()); result2 = FPMulAdd(Elem[operand3,e*2+1,esize],element4,element3,StandardFPSCRValue()); Elem[D[d+r],e*2,esize] = result1; Elem[D[d+r],e*2+1,esize] = result2;


Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

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