VCVT (between floating-point and fixed-point, Advanced SIMD)

Vector Convert between floating-point and fixed-point converts each element in a vector from floating-point to fixed-point, or from fixed-point to floating-point, and places the results in a second vector.

The vector elements are the same type, and are floating-point numbers or integers. Signed and unsigned integers are distinct.

The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

if imm6 IN {'000xxx'} then SEE "Related encodings"; if op<1> == '0' && !HaveFP16Ext() then UNDEFINED; if op<1> == '0' && imm6 IN {'10xxxx'} then UNDEFINED; if imm6 IN {'0xxxxx'} then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; to_fixed = (op<0> == '1'); frac_bits = 64 - UInt(imm6); unsigned = (U == '1'); integer esize; integer elements; case op<1> of when '0' esize = 16; elements = 4; when '1' esize = 32; elements = 2; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;

T1

if imm6 IN {'000xxx'} then SEE "Related encodings"; if op<1> == '0' && !HaveFP16Ext() then UNDEFINED; if op<1> == '0' && imm6 IN {'10xxxx'} then UNDEFINED; if imm6 IN {'0xxxxx'} then UNDEFINED; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; to_fixed = (op<0> == '1'); frac_bits = 64 - UInt(imm6); unsigned = (U == '1'); integer esize; integer elements; case op<1> of when '0' esize = 16; elements = 4; when '1' esize = 32; elements = 2; d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;

Assembler Symbols