Convert between floating-point and fixed-point converts a value in a register from floating-point to fixed-point, or from fixed-point to floating-point. Software can specify the fixed-point value as either signed or unsigned.
The fixed-point value can be 16-bit or 32-bit. Conversions from fixed-point values take their operand from the low-order bits of the source register and ignore any remaining bits. Signed conversions to fixed-point values sign-extend the result value to the destination register width. Unsigned conversions to fixed-point values zero-extend the result value to the destination register width.
The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 1 | op | 1 | U | Vd | 1 | 0 | sf | sx | 1 | i | 0 | imm4 | ||||||||||
| cond | |||||||||||||||||||||||||||||||
if sf == '00' || (sf == '01' && !HaveFP16Ext()) then UNDEFINED; if sf == '01' && cond != '1110' then UNPREDICTABLE; to_fixed = (op == '1'); unsigned = (U == '1'); size = if sx == '0' then 16 else 32; frac_bits = size - UInt(imm4:i); integer fp_size; integer d; case sf of when '01' fp_size = 16; d = UInt(Vd:D); when '10' fp_size = 32; d = UInt(Vd:D); when '11' fp_size = 64; d = UInt(D:Vd); if frac_bits < 0 then UNPREDICTABLE;
If frac_bits < 0, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 1 | op | 1 | U | Vd | 1 | 0 | sf | sx | 1 | i | 0 | imm4 | |||||||
if sf == '00' || (sf == '01' && !HaveFP16Ext()) then UNDEFINED; if sf == '01' && InITBlock() then UNPREDICTABLE; to_fixed = (op == '1'); unsigned = (U == '1'); size = if sx == '0' then 16 else 32; frac_bits = size - UInt(imm4:i); integer fp_size; integer d; case sf of when '01' fp_size = 16; d = UInt(Vd:D); when '10' fp_size = 32; d = UInt(Vd:D); when '11' fp_size = 64; d = UInt(D:Vd); if frac_bits < 0 then UNPREDICTABLE;
If frac_bits < 0, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VCVT (between floating-point and fixed-point).
| <c> |
| <q> |
| <dt> |
Is the data type for the fixed-point number,
encoded in
|
| <Sdm> |
Is the 32-bit name of the SIMD&FP destination and source register, encoded in the "Vd:D" field. |
| <Ddm> |
Is the 64-bit name of the SIMD&FP destination and source register, encoded in the "D:Vd" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); if to_fixed then bits(size) result; case fp_size of when 16 result = FPToFixed(S[d]<15:0>, frac_bits, unsigned, FPSCR[], FPRounding_ZERO, size); S[d] = Extend(result, 32, unsigned); when 32 result = FPToFixed(S[d], frac_bits, unsigned, FPSCR[], FPRounding_ZERO, size); S[d] = Extend(result, 32, unsigned); when 64 result = FPToFixed(D[d], frac_bits, unsigned, FPSCR[], FPRounding_ZERO, size); D[d] = Extend(result, 64, unsigned); else case fp_size of when 16 bits(16) fp16 = FixedToFP(S[d]<size-1:0>, frac_bits, unsigned, FPSCR[], FPRounding_TIEEVEN, 16); S[d] = Zeros(16):fp16; when 32 S[d] = FixedToFP(S[d]<size-1:0>, frac_bits, unsigned, FPSCR[], FPRounding_TIEEVEN, 32); when 64 D[d] = FixedToFP(D[d]<size-1:0>, frac_bits, unsigned, FPSCR[], FPRounding_TIEEVEN, 64);
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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