Converts the single-precision value in a single-precision register to BFloat16 format and writes the result into the bottom half of a single precision register, preserving the top 16 bits of the destination register.
Unlike the BFloat16 multiplication instructions, this instruction honors all the control bits in the FPSCR that apply to single-precision arithmetic, including the rounding mode. This instruction can generate a floating-point exception which causes a cumulative exception bit in the FPSCR to be set, or a synchronous exception to be taken, depending on the enable bits in the FPSCR.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 1 | 1 | Vd | 1 | 0 | 0 | 1 | 0 | 1 | M | 0 | Vm | |||||||||
| cond | |||||||||||||||||||||||||||||||
if !HaveAArch32BF16Ext() then UNDEFINED; integer d = UInt(Vd:D); integer m = UInt(Vm:M);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | D | 1 | 1 | 0 | 0 | 1 | 1 | Vd | 1 | 0 | 0 | 1 | 0 | 1 | M | 0 | Vm | ||||||
if !HaveAArch32BF16Ext() then UNDEFINED; integer d = UInt(Vd:D); integer m = UInt(Vm:M);
| <c> |
| <q> |
| <Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field. |
| <Sm> |
Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); S[d]<15:0> = FPConvertBF(S[m], FPSCR[]);
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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