Duplicate vector element to vector duplicates a single element of a vector into every element of the destination vector.
The scalar, and the destination vector elements, can be any one of 8-bit, 16-bit, or 32-bit fields. There is no distinction between data types.
For more information about scalars see Advanced SIMD scalars.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | D | 1 | 1 | imm4 | Vd | 1 | 1 | 0 | 0 | 0 | Q | M | 0 | Vm |
if imm4 IN {'x000'} then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; integer esize; integer elements; integer index; case imm4 of when 'xxx1' esize = 8; elements = 8; index = UInt(imm4<3:1>); when 'xx10' esize = 16; elements = 4; index = UInt(imm4<3:2>); when 'x100' esize = 32; elements = 2; index = UInt(imm4<3>); d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | D | 1 | 1 | imm4 | Vd | 1 | 1 | 0 | 0 | 0 | Q | M | 0 | Vm |
if imm4 IN {'x000'} then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; integer esize; integer elements; integer index; case imm4 of when 'xxx1' esize = 8; elements = 8; index = UInt(imm4<3:1>); when 'xx10' esize = 16; elements = 4; index = UInt(imm4<3:2>); when 'x100' esize = 32; elements = 2; index = UInt(imm4<3>); d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
<c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
For encoding T1: see Standard assembler syntax fields. |
<q> |
<Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
<Dm[x]> |
The scalar. For details of how [x] is encoded, see the description of <size>. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); scalar = Elem[D[m],index,esize]; for r = 0 to regs-1 for e = 0 to elements-1 Elem[D[d+r],e,esize] = scalar;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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