VFMAL (by scalar)

Vector Floating-point Multiply-Add Long to accumulator (by scalar). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_FHM)

if !HaveFP16MulNoRoundingToFP32Ext() then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; integer d = UInt(D:Vd); integer n = if Q == '1' then UInt(N:Vn) else UInt(Vn:N); integer m = if Q == '1' then UInt(Vm<2:0>) else UInt(Vm<2:0>:M); integer index = if Q == '1' then UInt(M:Vm<3>) else UInt(Vm<3>); integer esize = 32; integer regs = if Q=='1' then 2 else 1; integer datasize = if Q=='1' then 64 else 32; boolean sub_op = S=='1';

T1
(FEAT_FHM)

if InITBlock() then UNPREDICTABLE; if !HaveFP16MulNoRoundingToFP32Ext() then UNDEFINED; if Q == '1' && Vd<0> == '1' then UNDEFINED; integer d = UInt(D:Vd); integer n = if Q == '1' then UInt(N:Vn) else UInt(Vn:N); integer m = if Q == '1' then UInt(Vm<2:0>) else UInt(Vm<2:0>:M); integer index = if Q == '1' then UInt(M:Vm<3>) else UInt(Vm<3>); integer esize = 32; integer regs = if Q=='1' then 2 else 1; integer datasize = if Q=='1' then 64 else 32; boolean sub_op = S=='1';