VLD4 (multiple 4-element structures) -- AArch32

Load multiple 4-element structures to four registers loads multiple 4-element structures from memory into four registers, with de-interleaving. For more information, see Element and structure load/store instructions. Every element of each register is loaded. For details of the addressing mode, see Advanced SIMD addressing mode.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

integer inc; case itype of when '0000' inc = 1; when '0001' inc = 2; otherwise SEE "Related encodings"; if size == '11' then UNDEFINED; alignment = if align == '00' then 1 else 4 << UInt(align); ebytes = 1 << UInt(size); elements = 8 DIV ebytes; d = UInt(D:Vd); d2 = d + inc; d3 = d2 + inc; d4 = d3 + inc; n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d4 > 31 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD4 (multiple 4-element structures).

Related encodings: See Advanced SIMD element or structure load/store for the T32 instruction set, or Advanced SIMD element or structure load/store for the A32 instruction set.

Assembler Symbols

<c>	For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional.
	For encoding T1: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<size>

Is the data size, encoded in size:

size	<size>
00	8
01	16
10	32
11	RESERVED

<list>

Is a list containing the 64-bit names of the SIMD&FP registers.

The list must be one of:

{ <Dd>, <Dd+1>, <Dd+2>, <Dd+3> }: Single-spaced registers, encoded in the "itype" field as 0b0000.
{ <Dd>, <Dd+2>, <Dd+4>, <Dd+6> }: Double-spaced registers, encoded in the "itype" field as 0b0001.

The register <Dd> is encoded in the "D:Vd" field.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

<align>

Is the optional alignment.

Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and is encoded in the "align" field as 0b00.

Whenever <align> is present, the permitted values are:

64: 64-bit alignment, encoded in the "align" field as 0b01.
128: 128-bit alignment, encoded in the "align" field as 0b10.
256: 256-bit alignment, encoded in the "align" field as 0b11.

: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode.

<Rm>	Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); address = R[n]; boolean nontemporal = FALSE; boolean tagchecked = FALSE; AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked); if !IsAligned(address, alignment) then AArch32.Abort(address, AlignmentFault(accdesc)); for e = 0 to elements-1 Elem[D[d], e,8*ebytes] = MemU[address,ebytes]; Elem[D[d2],e,8*ebytes] = MemU[address+ebytes,ebytes]; Elem[D[d3],e,8*ebytes] = MemU[address+2*ebytes,ebytes]; Elem[D[d4],e,8*ebytes] = MemU[address+3*ebytes,ebytes]; address = address + 4*ebytes; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + 32;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06