Load Multiple SIMD&FP registers loads multiple registers from consecutive locations in the Advanced SIMD and floating-point register file using an address from a general-purpose register.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.
This instruction is used by the alias VPOP.
It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 0 | P | U | D | W | 1 | Rn | Vd | 1 | 0 | 1 | 1 | imm8<7:1> | 0 | |||||||||||||||
| cond | imm8<0> | ||||||||||||||||||||||||||||||
if P == '0' && U == '0' && W == '0' then SEE "Related encodings"; if P == '1' && W == '0' then SEE "VLDR"; if P == U && W == '1' then UNDEFINED; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) single_regs = FALSE; add = (U == '1'); wback = (W == '1'); d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see "FLDM*X". if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE; if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; if imm8<0> == '1' && (d+regs) > 16 then UNPREDICTABLE;
If regs == 0, then one of the following behaviors must occur:
If regs > 16 || (d+regs) > 32, then one of the following behaviors must occur:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| != 1111 | 1 | 1 | 0 | P | U | D | W | 1 | Rn | Vd | 1 | 0 | 1 | 0 | imm8 | ||||||||||||||||
| cond | |||||||||||||||||||||||||||||||
if P == '0' && U == '0' && W == '0' then SEE "Related encodings"; if P == '1' && W == '0' then SEE "VLDR"; if P == U && W == '1' then UNDEFINED; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) single_regs = TRUE; add = (U == '1'); wback = (W == '1'); d = UInt(Vd:D); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8); if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE; if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
If regs == 0, then one of the following behaviors must occur:
If (d+regs) > 32, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | P | U | D | W | 1 | Rn | Vd | 1 | 0 | 1 | 1 | imm8<7:1> | 0 | ||||||||||||
| imm8<0> | |||||||||||||||||||||||||||||||
if P == '0' && U == '0' && W == '0' then SEE "Related encodings"; if P == '1' && W == '0' then SEE "VLDR"; if P == U && W == '1' then UNDEFINED; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) single_regs = FALSE; add = (U == '1'); wback = (W == '1'); d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see "FLDM*X". if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE; if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE; if imm8<0> == '1' && (d+regs) > 16 then UNPREDICTABLE;
If regs == 0, then one of the following behaviors must occur:
If regs > 16 || (d+regs) > 32, then one of the following behaviors must occur:
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | P | U | D | W | 1 | Rn | Vd | 1 | 0 | 1 | 0 | imm8 | |||||||||||||
if P == '0' && U == '0' && W == '0' then SEE "Related encodings"; if P == '1' && W == '0' then SEE "VLDR"; if P == U && W == '1' then UNDEFINED; // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !) single_regs = TRUE; add = (U == '1'); wback = (W == '1'); d = UInt(Vd:D); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8); if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE; if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
If regs == 0, then one of the following behaviors must occur:
If (d+regs) > 32, then one of the following behaviors must occur:
For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLDM.
Related encodings: See Advanced SIMD and floating-point 64-bit move for the T32 instruction set, or Advanced SIMD and floating-point 64-bit move for the A32 instruction set.
| <c> |
| <q> |
| <size> |
An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred. |
| <Rn> |
Is the general-purpose base register, encoded in the "Rn" field. If writeback is not specified, the PC can be used. |
| ! |
Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0. |
| Alias | Is preferred when |
|---|---|
| VPOP | P == '0' && U == '1' && W == '1' && Rn == '1101' |
if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); address = if add then R[n] else R[n]-imm32; for r = 0 to regs-1 if single_regs then S[d+r] = MemA[address,4]; address = address+4; else word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8; // Combine the word-aligned words in the correct order for current endianness. D[d+r] = if BigEndian(AccessType_ASIMD) then word1:word2 else word2:word1; if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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