Vector Move Long takes each element in a doubleword vector, sign or zero-extends them to twice their original length, and places the results in a quadword vector.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | U | 1 | D | != 000 | 0 | 0 | 0 | Vd | 1 | 0 | 1 | 0 | 0 | 0 | M | 1 | Vm | ||||||||
| imm3H | |||||||||||||||||||||||||||||||
if imm3H == '000' then SEE "Related encodings"; if imm3H != '001' && imm3H != '010' && imm3H != '100' then SEE "VSHLL"; if Vd<0> == '1' then UNDEFINED; esize = 8 * UInt(imm3H); unsigned = (U == '1'); elements = 64 DIV esize; d = UInt(D:Vd); m = UInt(M:Vm);
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | U | 1 | 1 | 1 | 1 | 1 | D | != 000 | 0 | 0 | 0 | Vd | 1 | 0 | 1 | 0 | 0 | 0 | M | 1 | Vm | ||||||||
| imm3H | |||||||||||||||||||||||||||||||
if imm3H == '000' then SEE "Related encodings"; if imm3H != '001' && imm3H != '010' && imm3H != '100' then SEE "VSHLL"; if Vd<0> == '1' then UNDEFINED; esize = 8 * UInt(imm3H); unsigned = (U == '1'); elements = 64 DIV esize; d = UInt(D:Vd); m = UInt(M:Vm);
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <dt> |
Is the data type for the elements of the operand,
encoded in
|
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for e = 0 to elements-1 result = Int(Elem[Din[m],e,esize], unsigned); Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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