Vector Bitwise NOT (immediate) places the bitwise inverse of an immediate integer constant into every element of the destination register.
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 , A2 and A3 ) and T32 ( T1 , T2 and T3 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | i | 1 | D | 0 | 0 | 0 | imm3 | Vd | 0 | x | x | 0 | 0 | Q | 1 | 1 | imm4 | ||||||||
| cmode | |||||||||||||||||||||||||||||||
if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | i | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 0 | x | 0 | 0 | Q | 1 | 1 | imm4 | ||||||||
| cmode | |||||||||||||||||||||||||||||||
if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | i | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 1 | 0 | x | 0 | Q | 1 | 1 | imm4 | ||||||||
| cmode | |||||||||||||||||||||||||||||||
if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | i | 1 | 1 | 1 | 1 | 1 | D | 0 | 0 | 0 | imm3 | Vd | 0 | x | x | 0 | 0 | Q | 1 | 1 | imm4 | ||||||||
| cmode | |||||||||||||||||||||||||||||||
if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | i | 1 | 1 | 1 | 1 | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 0 | x | 0 | 0 | Q | 1 | 1 | imm4 | ||||||||
| cmode | |||||||||||||||||||||||||||||||
if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | i | 1 | 1 | 1 | 1 | 1 | D | 0 | 0 | 0 | imm3 | Vd | 1 | 1 | 0 | x | 0 | Q | 1 | 1 | imm4 | ||||||||
| cmode | |||||||||||||||||||||||||||||||
if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings"; if Q == '1' && Vd<0> == '1' then UNDEFINED; imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4); d = UInt(D:Vd); regs = if Q == '0' then 1 else 2;
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
| <c> |
For encoding A1, A2 and A3: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1, T2 and T3: see Standard assembler syntax fields. |
| <q> |
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <imm> |
Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in T32 and A32 Advanced SIMD instructions. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for r = 0 to regs-1 D[d+r] = NOT(imm64);
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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