VNMLS

Vector Negate Multiply Subtract multiplies together two floating-point register values, adds the negation of the floating-point value in the destination register to the product, and writes the result back to the destination register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111111100D01VnVd10sizeN0M0Vm
condop

Half-precision scalar (size == 01)
(FEAT_FP16)

VNMLS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm>

Single-precision scalar (size == 10)

VNMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>

Double-precision scalar (size == 11)

VNMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>

if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && cond != '1110' then UNPREDICTABLE; vtype = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS; integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111011100D01VnVd10sizeN0M0Vm
op

Half-precision scalar (size == 01)
(FEAT_FP16)

VNMLS{<c>}{<q>}.F16 <Sd>, <Sn>, <Sm>

Single-precision scalar (size == 10)

VNMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>

Double-precision scalar (size == 11)

VNMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>

if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; if size == '01' && InITBlock() then UNPREDICTABLE; vtype = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS; integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && InITBlock(), then one of the following behaviors must occur:

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>

Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>

Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); case esize of when 16 product16 = FPMul(S[n]<15:0>, S[m]<15:0>, FPSCR[]); case vtype of when VFPNegMul_VNMLA S[d] = (Zeros(16) : FPAdd(FPNeg(S[d]<15:0>), FPNeg(product16), FPSCR[])); when VFPNegMul_VNMLS S[d] = (Zeros(16) : FPAdd(FPNeg(S[d]<15:0>), product16, FPSCR[])); when VFPNegMul_VNMUL S[d] = Zeros(16) : FPNeg(product16); when 32 product32 = FPMul(S[n], S[m], FPSCR[]); case vtype of when VFPNegMul_VNMLA S[d] = FPAdd(FPNeg(S[d]), FPNeg(product32), FPSCR[]); when VFPNegMul_VNMLS S[d] = FPAdd(FPNeg(S[d]), product32, FPSCR[]); when VFPNegMul_VNMUL S[d] = FPNeg(product32); when 64 product64 = FPMul(D[n], D[m], FPSCR[]); case vtype of when VFPNegMul_VNMLA D[d] = FPAdd(FPNeg(D[d]), FPNeg(product64), FPSCR[]); when VFPNegMul_VNMLS D[d] = FPAdd(FPNeg(D[d]), product64, FPSCR[]); when VFPNegMul_VNMUL D[d] = FPNeg(product64);


Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.