VRINTA (floating-point)

Round floating-point to integer to Nearest with Ties to Away rounds a floating-point value to an integral floating-point value of the same size using the Round to Nearest with Ties to Away rounding mode. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111111101D111000Vd10!= 0001M0Vm
RMsize

Half-precision scalar (size == 01)
(FEAT_FP16)

VRINTA{<q>}.F16 <Sd>, <Sm>

Single-precision scalar (size == 10)

VRINTA{<q>}.F32 <Sd>, <Sm>

Double-precision scalar (size == 11)

VRINTA{<q>}.F64 <Dd>, <Dm>

if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; rounding = FPDecodeRM(RM); exact = FALSE; integer esize; integer d; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);

T1

15141312111098765432101514131211109876543210
111111101D111000Vd10!= 0001M0Vm
RMsize

Half-precision scalar (size == 01)
(FEAT_FP16)

VRINTA{<q>}.F16 <Sd>, <Sm>

Single-precision scalar (size == 10)

VRINTA{<q>}.F32 <Sd>, <Sm>

Double-precision scalar (size == 11)

VRINTA{<q>}.F64 <Dd>, <Dm>

if InITBlock() then UNPREDICTABLE; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; rounding = FPDecodeRM(RM); exact = FALSE; integer esize; integer d; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); m = UInt(M:Vm);

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<q>

See Standard assembler syntax fields.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

Operation

EncodingSpecificOperations(); CheckVFPEnabled(TRUE); case esize of when 16 S[d] = Zeros(16) : FPRoundInt(S[m]<15:0>, FPSCR[], rounding, exact); when 32 S[d] = FPRoundInt(S[m], FPSCR[], rounding, exact); when 64 D[d] = FPRoundInt(D[m], FPSCR[], rounding, exact);


Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.