Vector Rounding Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate value, and accumulates the rounded results into the destination vector. For truncated results, see VSRA.
The operand and result elements must all be the same type, and can be any one of:
Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | U | 1 | D | imm6 | Vd | 0 | 0 | 1 | 1 | L | Q | M | 1 | Vm | |||||||||||
if (L:imm6) IN {'0000xxx'} then SEE "Related encodings"; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; integer esize; integer elements; integer shift_amount; case L:imm6 of when '0001xxx' esize = 8; elements = 8; shift_amount = 16 - UInt(imm6); when '001xxxx' esize = 16; elements = 4; shift_amount = 32 - UInt(imm6); when '01xxxxx' esize = 32; elements = 2; shift_amount = 64 - UInt(imm6); when '1xxxxxx' esize = 64; elements = 1; shift_amount = 64 - UInt(imm6); unsigned = (U == '1'); d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | U | 1 | 1 | 1 | 1 | 1 | D | imm6 | Vd | 0 | 0 | 1 | 1 | L | Q | M | 1 | Vm | |||||||||||
if (L:imm6) IN {'0000xxx'} then SEE "Related encodings"; if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED; integer esize; integer elements; integer shift_amount; case L:imm6 of when '0001xxx' esize = 8; elements = 8; shift_amount = 16 - UInt(imm6); when '001xxxx' esize = 16; elements = 4; shift_amount = 32 - UInt(imm6); when '01xxxxx' esize = 32; elements = 2; shift_amount = 64 - UInt(imm6); when '1xxxxxx' esize = 64; elements = 1; shift_amount = 64 - UInt(imm6); unsigned = (U == '1'); d = UInt(D:Vd); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.
| <c> |
For encoding A1: see Standard assembler syntax fields. This encoding must be unconditional. |
|
For encoding T1: see Standard assembler syntax fields. |
| <q> |
| <type> |
Is the data type for the elements of the vectors,
encoded in
|
| <size> |
Is the data size for the elements of the vectors,
encoded in
|
| <Qd> |
Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2. |
| <Qm> |
Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2. |
| <Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field. |
| <Dm> |
Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field. |
| <imm> |
Is an immediate value, in the range 1 to <size>, encoded in the "imm6" field as <size> - <imm>. |
if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); boolean round = TRUE; for r = 0 to regs-1 for e = 0 to elements-1 result = RShr(Int(Elem[D[m+r],e,esize], unsigned), shift_amount, round); Elem[D[d+r],e,esize] = Elem[D[d+r],e,esize] + result;
If CPSR.DIT is 1 and this instruction passes its condition execution check:
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06
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