VSELEQ, VSELGE, VSELGT, VSELVS

Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the APSR.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111111100DccVnVd10!= 00N0M0Vm
size

Equal, half-precision scalar (cc == 00 && size == 01)
(FEAT_FP16)

VSELEQ.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Equal, single-precision scalar (cc == 00 && size == 10)

VSELEQ.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Equal, double-precision scalar (cc == 00 && size == 11)

VSELEQ.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)

Greater than or Equal, half-precision scalar (cc == 10 && size == 01)
(FEAT_FP16)

VSELGE.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Greater than or Equal, single-precision scalar (cc == 10 && size == 10)

VSELGE.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Greater than or Equal, double-precision scalar (cc == 10 && size == 11)

VSELGE.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)

Greater than, half-precision scalar (cc == 11 && size == 01)
(FEAT_FP16)

VSELGT.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Greater than, single-precision scalar (cc == 11 && size == 10)

VSELGT.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Greater than, double-precision scalar (cc == 11 && size == 11)

VSELGT.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)

Unordered, half-precision scalar (cc == 01 && size == 01)
(FEAT_FP16)

VSELVS.F16 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Unordered, single-precision scalar (cc == 01 && size == 10)

VSELVS.F32 <Sd>, <Sn>, <Sm> // (Cannot be conditional)

Unordered, double-precision scalar (cc == 01 && size == 11)

VSELVS.F64 <Dd>, <Dn>, <Dm> // (Cannot be conditional)

if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); cond = cc:(cc<1> EOR cc<0>):'0';

T1

15141312111098765432101514131211109876543210
111111100DccVnVd10!= 00N0M0Vm
size

Equal, half-precision scalar (cc == 00 && size == 01)
(FEAT_FP16)

VSELEQ.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Equal, single-precision scalar (cc == 00 && size == 10)

VSELEQ.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Equal, double-precision scalar (cc == 00 && size == 11)

VSELEQ.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)

Greater than or Equal, half-precision scalar (cc == 10 && size == 01)
(FEAT_FP16)

VSELGE.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Greater than or Equal, single-precision scalar (cc == 10 && size == 10)

VSELGE.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Greater than or Equal, double-precision scalar (cc == 10 && size == 11)

VSELGE.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)

Greater than, half-precision scalar (cc == 11 && size == 01)
(FEAT_FP16)

VSELGT.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Greater than, single-precision scalar (cc == 11 && size == 10)

VSELGT.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Greater than, double-precision scalar (cc == 11 && size == 11)

VSELGT.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)

Unordered, half-precision scalar (cc == 01 && size == 01)
(FEAT_FP16)

VSELVS.F16 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Unordered, single-precision scalar (cc == 01 && size == 10)

VSELVS.F32 <Sd>, <Sn>, <Sm> // (Not permitted in IT block)

Unordered, double-precision scalar (cc == 01 && size == 11)

VSELVS.F64 <Dd>, <Dn>, <Dm> // (Not permitted in IT block)

if InITBlock() then UNPREDICTABLE; if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED; integer esize; integer d; integer n; integer m; case size of when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M); when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); cond = cc:(cc<1> EOR cc<0>):'0';

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

Assembler Symbols

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>

Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>

Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

Operation

EncodingSpecificOperations(); CheckVFPEnabled(TRUE); case esize of when 16 S[d] = Zeros(16) : (if ConditionHolds(cond) then S[n] else S[m])<15:0>; when 32 S[d] = if ConditionHolds(cond) then S[n] else S[m]; when 64 D[d] = if ConditionHolds(cond) then D[n] else D[m];


Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.