VSELEQ, VSELGE, VSELGT, VSELVS
Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the APSR.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
)
.
A1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | cc | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm |
| | | | | | size | | | | | |
Equal, half-precision scalar (cc == 00 && size == 01)
(FEAT_FP16)
VSELEQ.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Equal, single-precision scalar (cc == 00 && size == 10)
VSELEQ.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Equal, double-precision scalar (cc == 00 && size == 11)
VSELEQ.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
Greater than or Equal, half-precision scalar (cc == 10 && size == 01)
(FEAT_FP16)
VSELGE.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Greater than or Equal, single-precision scalar (cc == 10 && size == 10)
VSELGE.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Greater than or Equal, double-precision scalar (cc == 10 && size == 11)
VSELGE.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
Greater than, half-precision scalar (cc == 11 && size == 01)
(FEAT_FP16)
VSELGT.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Greater than, single-precision scalar (cc == 11 && size == 10)
VSELGT.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Greater than, double-precision scalar (cc == 11 && size == 11)
VSELGT.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
Unordered, half-precision scalar (cc == 01 && size == 01)
(FEAT_FP16)
VSELVS.F16 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Unordered, single-precision scalar (cc == 01 && size == 10)
VSELVS.F32 <Sd>, <Sn>, <Sm>
//
(Cannot be conditional)
Unordered, double-precision scalar (cc == 01 && size == 11)
VSELVS.F64 <Dd>, <Dn>, <Dm>
//
(Cannot be conditional)
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
integer esize;
integer d;
integer n;
integer m;
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
cond = cc:(cc<1> EOR cc<0>):'0';
T1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | D | cc | Vn | Vd | 1 | 0 | != 00 | N | 0 | M | 0 | Vm |
| | | | | | size | | | | | |
Equal, half-precision scalar (cc == 00 && size == 01)
(FEAT_FP16)
VSELEQ.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Equal, single-precision scalar (cc == 00 && size == 10)
VSELEQ.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Equal, double-precision scalar (cc == 00 && size == 11)
VSELEQ.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
Greater than or Equal, half-precision scalar (cc == 10 && size == 01)
(FEAT_FP16)
VSELGE.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Greater than or Equal, single-precision scalar (cc == 10 && size == 10)
VSELGE.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Greater than or Equal, double-precision scalar (cc == 10 && size == 11)
VSELGE.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
Greater than, half-precision scalar (cc == 11 && size == 01)
(FEAT_FP16)
VSELGT.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Greater than, single-precision scalar (cc == 11 && size == 10)
VSELGT.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Greater than, double-precision scalar (cc == 11 && size == 11)
VSELGT.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
Unordered, half-precision scalar (cc == 01 && size == 01)
(FEAT_FP16)
VSELVS.F16 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Unordered, single-precision scalar (cc == 01 && size == 10)
VSELVS.F32 <Sd>, <Sn>, <Sm>
//
(Not permitted in IT block)
Unordered, double-precision scalar (cc == 01 && size == 11)
VSELVS.F64 <Dd>, <Dn>, <Dm>
//
(Not permitted in IT block)
if InITBlock() then UNPREDICTABLE;
if size == '00' || (size == '01' && !HaveFP16Ext()) then UNDEFINED;
integer esize;
integer d;
integer n;
integer m;
case size of
when '01' esize = 16; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '10' esize = 32; d = UInt(Vd:D); n = UInt(Vn:N); m = UInt(Vm:M);
when '11' esize = 64; d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
cond = cc:(cc<1> EOR cc<0>):'0';
CONSTRAINED UNPREDICTABLE behavior
If InITBlock(), then one of the following behaviors must occur:
- The instruction is undefined.
- The instruction executes as if it passes the Condition code check.
- The instruction executes as NOP. This means it behaves as if it fails the Condition code check.
Assembler Symbols
<Dd> |
Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
|
<Dn> |
Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.
|
<Dm> |
Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
|
<Sd> |
Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
|
<Sn> |
Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.
|
<Sm> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.
|
Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel
; Build timestamp: 2023-07-04T18:06
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