VST4 (single 4-element structure from one lane) -- AArch32

Store single 4-element structure from one lane of four registers stores one 4-element structure to memory from corresponding elements of four registers. For details of the addressing mode, see Advanced SIMD addressing mode.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 , A2 and A3 ) and T32 ( T1 , T2 and T3 ) .

if size == '11' then UNDEFINED; if size != '00' then SEE "Related encodings"; ebytes = 1; index = UInt(index_align<3:1>); inc = 1; alignment = if index_align<0> == '0' then 1 else 4; d = UInt(D:Vd); d2 = d + inc; d3 = d2 + inc; d4 = d3 + inc; n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d4 > 31 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

if size == '11' then UNDEFINED; if size != '01' then SEE "Related encodings"; ebytes = 2; index = UInt(index_align<3:2>); inc = if index_align<1> == '0' then 1 else 2; alignment = if index_align<0> == '0' then 1 else 8; d = UInt(D:Vd); d2 = d + inc; d3 = d2 + inc; d4 = d3 + inc; n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d4 > 31 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

if size == '11' then UNDEFINED; if size != '10' then SEE "Related encodings"; if index_align<1:0> == '11' then UNDEFINED; ebytes = 4; index = UInt(index_align<3>); inc = if index_align<2> == '0' then 1 else 2; alignment = if index_align<1:0> == '00' then 1 else 4 << UInt(index_align<1:0>); d = UInt(D:Vd); d2 = d + inc; d3 = d2 + inc; d4 = d3 + inc; n = UInt(Rn); m = UInt(Rm); wback = (m != 15); register_index = (m != 15 && m != 13); if n == 15 || d4 > 31 then UNPREDICTABLE;

CONSTRAINED UNPREDICTABLE behavior

Assembler Symbols

<c>	For encoding A1, A2 and A3: see Standard assembler syntax fields. This encoding must be unconditional.
	For encoding T1, T2 and T3: see Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<size>

Is the data size, encoded in size:

size	<size>
00	8
01	16
10	32

<list>

Is a list containing the 64-bit names of the four SIMD&FP registers holding the element.

The list must be one of:

{ <Dd>[<index>], <Dd+1>[<index>], <Dd+2>[<index>], <Dd+3>[<index>] }: Single-spaced registers, encoded as "spacing" = 0.
{ <Dd>[<index>], <Dd+2>[<index>], <Dd+4>[<index>], <Dd+6>[<index>] }: Double-spaced registers, encoded as "spacing" = 1. Not permitted when <size> == 8.

The encoding of "spacing" depends on <size>:

<size> == 16: "spacing" is encoded in the "index_align<1>" field.
<size> == 32: "spacing" is encoded in the "index_align<2>" field.

The register <Dd> is encoded in the "D:Vd" field.

The permitted values and encoding of <index> depend on <size>:

<size> == 8: <index> is in the range 0 to 7, encoded in the "index_align<3:1>" field.
<size> == 16: <index> is in the range 0 to 3, encoded in the "index_align<3:2>" field.
<size> == 32: <index> is 0 or 1, encoded in the "index_align<3>" field.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

<align>

Is the optional alignment.

Whenever <align> is omitted, the standard alignment is used, see Unaligned data access, and the encoding depends on <size>:

<size> == 8: Encoded in the "index_align<0>" field as 0.
<size> == 16: Encoded in the "index_align<0>" field as 0.
<size> == 32: Encoded in the "index_align<1:0>" field as 0b00.

Whenever <align> is present, the permitted values and encoding depend on <size>:

<size> == 8: <align> is 32, meaning 32-bit alignment, encoded in the "index_align<0>" field as 1.
<size> == 16: <align> is 64, meaning 64-bit alignment, encoded in the "index_align<0>" field as 1.
<size> == 32: <align> can be 64 or 128. 64-bit alignment is encoded in the "index_align<1:0>" field as 0b01, and 128-bit alignment is encoded in the "index_align<1:0>" field as 0b10.

: is the preferred separator before the <align> value, but the alignment can be specified as @<align>, see Advanced SIMD addressing mode.

<Rm>	Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); address = R[n]; boolean nontemporal = FALSE; boolean tagchecked = FALSE; AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked); if !IsAligned(address, alignment) then AArch32.Abort(address, AlignmentFault(accdesc)); MemU[address, ebytes] = Elem[D[d], index,8*ebytes]; MemU[address+ebytes, ebytes] = Elem[D[d2],index,8*ebytes]; MemU[address+2*ebytes,ebytes] = Elem[D[d3],index,8*ebytes]; MemU[address+3*ebytes,ebytes] = Elem[D[d4],index,8*ebytes]; if wback then if register_index then R[n] = R[n] + R[m]; else R[n] = R[n] + 4*ebytes;

Operational information

If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: isa v01_31, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T18:06