Branch Record Buffer. For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.
This is an alias of SYS. This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | op2 | Rt | ||||||
| L | op1 | CRn | CRm | ||||||||||||||||||||||||||||
is equivalent to
SYS #1, C7, C2, #<op2>{, <Xt>}
and is the preferred disassembly when SysOp('001','0111','0010',op2) == Sys_BRB.
| <brb_op> |
Is a BRB instruction name, as listed for the BRB system instruction group,
encoded in
|
| <op2> |
Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field. |
| <Xt> |
Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field. |
The description of SYS gives the operational pseudocode for this instruction.
Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42
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