Signed saturating unsigned extract narrow and interleave
Saturate the signed integer value in each element of the group of two source vectors to unsigned integer value that is half the original source element width, and place the two-way interleaved results in the half-width destination elements.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | Zn | 0 | Zd | |||||||
| tszh | tszl<1> | tszl<0> | |||||||||||||||||||||||||||||
if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; constant integer esize = 16; integer n = UInt(Zn:'0'); integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2. |
| <Zn2> |
Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV (2 * esize); bits(VL) result; for e = 0 to elements-1 for i = 0 to 1 bits(VL) operand = Z[n+i, VL]; integer element = SInt(Elem[operand, e, 2 * esize]); Elem[result, 2*e + i, esize] = UnsignedSat(element, esize); Z[d, VL] = result;
Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42
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