Multi-vector unsigned clamp to minimum/maximum vector
Clamp each unsigned element in the two or four destination vectors to between the unsigned minimum value in the corresponding element of the first source vector and the unsigned maximum value in the corresponding element of the second source vector and destructively place the clamped results in the corresponding elements of the two or four destination vectors.
This instruction is unpredicated.
It has encodings from 2 classes: Two registers and Four registers
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | size | 1 | Zm | 1 | 1 | 0 | 0 | 0 | 1 | Zn | Zd | 1 | ||||||||||||
| U | |||||||||||||||||||||||||||||||
if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd:'0'); constant integer nreg = 2;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | size | 1 | Zm | 1 | 1 | 0 | 0 | 1 | 1 | Zn | Zd | 0 | 1 | |||||||||||
| U | |||||||||||||||||||||||||||||||
if !HaveSME2() then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Zn); integer m = UInt(Zm); integer d = UInt(Zd:'00'); constant integer nreg = 4;
| <T> |
Is the size specifier,
encoded in
|
| <Zd4> |
Is the name of the fourth destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4 plus 3. |
| <Zd2> |
Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1. |
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; array [0..3] of bits(VL) results; for r = 0 to nreg-1 bits(VL) operand1 = Z[n, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) operand3 = Z[d+r, VL]; for e = 0 to elements-1 integer element1 = UInt(Elem[operand1, e, esize]); integer element2 = UInt(Elem[operand2, e, esize]); integer element3 = UInt(Elem[operand3, e, esize]); integer res = Min(Max(element1, element3), element2); Elem[results[r], e, esize] = res<esize-1:0>; for r = 0 to nreg-1 Z[d+r, VL] = results[r];
If PSTATE.DIT is 1:
Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42
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