The DBGBCR<n> characteristics are:
Holds control information for a breakpoint. Forms breakpoint n together with value register DBGBVR<n>. If EL2 is implemented and this breakpoint supports Context matching, DBGBVR<n> can be associated with a Breakpoint Extended Value Register DBGBXVR<n> for VMID matching.
AArch32 System register DBGBCR<n> bits [31:0] are architecturally mapped to AArch64 System register DBGBCR<n>_EL1[31:0].
AArch32 System register DBGBCR<n> bits [31:0] are architecturally mapped to External register DBGBCR<n>_EL1[31:0].
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to DBGBCR<n> are UNDEFINED.
If breakpoint n is not implemented then accesses to this register are UNDEFINED.
DBGBCR<n> is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | BT | LBN | SSC | HMC | RES0 | BAS | RES0 | PMC | E | ||||||||||||||||||||||
When the E field is zero, all the other fields in the register are ignored.
Reserved, RES0.
Breakpoint Type. Possible values are:
| BT | Meaning |
|---|---|
| 0b0000 |
Unlinked instruction address match. DBGBVR<n> is the address of an instruction. |
| 0b0001 |
As 0b0000, but linked to a Context matching breakpoint. |
| 0b0010 |
Unlinked Context ID match. When FEAT_VHE is implemented, EL2 is using AArch64, and the Effective value of HCR_EL2.E2H is 1, if either the PE is executing at EL0 with HCR_EL2.TGE set to 1 or the PE is executing at EL2, then DBGBVR<n>.ContextID must match the CONTEXTIDR_EL2 value. Otherwise, DBGBVR<n>.ContextID must match the CONTEXTIDR value. |
| 0b0011 |
As 0b0010 with linking enabled. |
| 0b0100 |
Unlinked instruction address mismatch. DBGBVR<n> is the address of an instruction to be stepped. |
| 0b0101 |
As 0b0100, but linked to a Context matching breakpoint. |
| 0b0110 |
Unlinked CONTEXTIDR_EL1 match. DBGBVR<n>.ContextID is a Context ID compared against CONTEXTIDR. |
| 0b0111 |
As 0b0110 with linking enabled. |
| 0b1000 |
Unlinked VMID match. DBGBXVR<n>.VMID is a VMID compared against VTTBR.VMID. |
| 0b1001 |
As 0b1000 with linking enabled. |
| 0b1010 |
Unlinked VMID and Context ID match. DBGBVR<n>.ContextID is a Context ID compared against CONTEXTIDR, and DBGBXVR<n>.VMID is a VMID compared against VTTBR.VMID. |
| 0b1011 |
As 0b1010 with linking enabled. |
| 0b1100 |
Unlinked CONTEXTIDR_EL2 match. DBGBXVR<n>.ContextID2 is a Context ID compared against CONTEXTIDR_EL2. |
| 0b1101 |
As 0b1100 with linking enabled. |
| 0b1110 |
Unlinked Full Context ID match. DBGBVR<n>.ContextID is compared against CONTEXTIDR, and DBGBXVR<n>.ContextID2 is compared against CONTEXTIDR_EL2. |
| 0b1111 |
As 0b1110 with linking enabled. |
For more information on Breakpoints and their constraints, see 'Breakpoint exceptions' and 'Reserved DBGBCR<n>.BT values'.
The reset behavior of this field is:
Linked Breakpoint Number. For Linked address matching breakpoints, this specifies the index of the Context-matching breakpoint linked to.
For all other breakpoint types, this field is ignored and reads of the register return an UNKNOWN value.
This field is ignored when the value of DBGBCR<n>.E is 0.
The reset behavior of this field is:
Security state control. Determines the Security states under which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the HMC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields.
For more information, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions' and 'Reserved DBGBCR<n>.{SSC, HMC, PMC} values'.
The reset behavior of this field is:
Higher mode control. Determines the debug perspective for deciding when a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and PMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the SSC, bits [15:14] description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
The reset behavior of this field is:
Reserved, RES0.
Byte address select. Defines which half-words an address-matching breakpoint matches, regardless of the instruction set and Execution state.
The permitted values depend on the breakpoint type.
For Address match breakpoints, the permitted values are:
| BAS | Match instruction at | Constraint for debuggers |
|---|---|---|
| 0b0011 | DBGBVR<n> | Use for T32 instructions |
| 0b1100 | DBGBVR<n>+2 | Use for T32 instructions |
| 0b1111 | DBGBVR<n> | Use for A32 instructions |
All other values are reserved. For more information, see 'Reserved DBGBCR<n>.BAS values'.
For more information on using the BAS field in Address Match breakpoints, see 'Using the BAS field in Address Match breakpoints'.
For Address mismatch breakpoints in an AArch32 stage 1 translation regime, the permitted values are:
| BAS | Step instruction at | Constraint for debuggers |
|---|---|---|
| 0b0000 | - | Use for a match anywhere breakpoint |
| 0b0011 | DBGBVR<n> | Use for T32 instructions |
| 0b1100 | DBGBVR<n>+2 | Use for T32 instructions |
| 0b1111 | DBGBVR<n> | Use for A32 instructions |
All other values are reserved. For more information, see 'Reserved DBGBCR<n>.BAS values'.
For more information on using the BAS field in address mismatch breakpoints, see 'Using the BAS field in Address Match breakpoints'.
For Context matching breakpoints, this field is RES1 and ignored.
The reset behavior of this field is:
Reserved, RES0.
Privilege mode control. Determines the Exception level or levels at which a Breakpoint debug event for breakpoint n is generated. This field must be interpreted along with the SSC and HMC fields, and there are constraints on the permitted values of the {HMC, SSC, PMC} fields. For more information see the DBGBCR<n>.SSC description.
For more information on the operation of the SSC, HMC, and PMC fields, see 'Execution conditions for which a breakpoint generates Breakpoint exceptions'.
The reset behavior of this field is:
Enable breakpoint DBGBVR<n>. Possible values are:
| E | Meaning |
|---|---|
| 0b0 |
Breakpoint disabled. |
| 0b1 |
Breakpoint enabled. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1110 | 0b000 | 0b0000 | m[3:0] | 0b101 |
integer m = UInt(CRm<3:0>); if m >= NUM_BREAKPOINTS then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R[t] = DBGBCR[m]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R[t] = DBGBCR[m]; elsif PSTATE.EL == EL3 then if DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else R[t] = DBGBCR[m];
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1110 | 0b000 | 0b0000 | m[3:0] | 0b101 |
integer m = UInt(CRm<3:0>); if m >= NUM_BREAKPOINTS then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBCR[m] = R[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); elsif DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBCR[m] = R[t]; elsif PSTATE.EL == EL3 then if DBGOSLSR.OSLK == '0' && HaltingAllowed() && EDSCR.TDA == '1' then Halt(DebugHalt_SoftwareAccess); else DBGBCR[m] = R[t];
04/07/2023 11:26; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.