The ID_PFR0 characteristics are:
Gives top-level information about the instruction sets and other features supported by the PE in AArch32 state.
Must be interpreted with ID_PFR1.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
AArch32 System register ID_PFR0 bits [31:0] are architecturally mapped to AArch64 System register ID_PFR0_EL1[31:0].
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_PFR0 are UNDEFINED.
ID_PFR0 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAS | DIT | AMU | CSV2 | State3 | State2 | State1 | State0 | ||||||||||||||||||||||||
RAS Extension version. Defined values are:
| RAS | Meaning |
|---|---|
| 0b0000 |
No RAS Extension. |
| 0b0001 |
RAS Extension implemented. |
| 0b0010 | FEAT_RASv1p1 implemented. As 0b0001, and adds support for additional ERXMISC<m> System registers. Error records accessed through System registers conform to RAS System Architecture v1.1, which includes simplifications to ERR<n>STATUS and support for the optional RAS Timestamp Extension. |
| 0b0011 |
FEAT_RASv2 implemented. As 0b0010, and requires that error records accessed through System registers conform to RAS System Architecture v2. |
All other values are reserved.
FEAT_RAS implements the functionality identified by the value 0b0001.
FEAT_RASv1p1 implements the functionality identified by the value 0b0010.
FEAT_RASv2 implements the functionality identified by the value 0b0011.
In Armv8.0 and Armv8.1, the permitted values are 0b0000 and 0b0001.
From Armv8.2, the value 0b0000 is not permitted.
From Armv8.4, if FEAT_DoubleFault is implemented or ERRIDR.NUM is nonzero, the value 0b0001 is not permitted.
When the value of this field is 0b0001, ID_PFR2.RAS_frac indicates whether FEAT_RASv1p1 is implemented.
From Armv8.9, the values 0b0001 and 0b0010 are not permitted.
Data Independent Timing. Defined values are:
| DIT | Meaning |
|---|---|
| 0b0000 |
AArch32 does not guarantee constant execution time of any instructions. |
| 0b0001 |
AArch32 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions. |
All other values are reserved.
FEAT_DIT implements the functionality identified by the value 0b0001.
From Armv8.4, the only permitted value is 0b0001.
Indicates support for Activity Monitors Extension. Defined values are:
| AMU | Meaning |
|---|---|
| 0b0000 |
Activity Monitors Extension is not implemented. |
| 0b0001 |
FEAT_AMUv1 is implemented. |
| 0b0010 |
FEAT_AMUv1p1 is implemented. As 0b0001 and adds support for virtualization of the activity monitor event counters. |
All other values are reserved.
FEAT_AMUv1 implements the functionality identified by the value 0b0001.
FEAT_AMUv1p1 implements the functionality identified by the value 0b0010.
In Armv8.0, the only permitted value is 0b0000.
In Armv8.4, the permitted values are 0b0000 and 0b0001.
From Armv8.6, the permitted values are 0b0000, 0b0001, and 0b0010.
Speculative use of out of context branch targets. Defined values are:
| CSV2 | Meaning |
|---|---|
| 0b0000 |
The implementation does not disclose whether FEAT_CSV2 is implemented. |
| 0b0001 |
FEAT_CSV2 is implemented, but FEAT_CSV2_1p1 is not implemented. |
| 0b0010 |
FEAT_CSV2_1p1 is implemented. |
All other values are reserved.
FEAT_CSV2 implements the functionality identified by the value 0b0001.
FEAT_CSV2_1p1 implements the functionality identified by the value 0b0010.
From Armv8.5, the permitted values are 0b0001 and 0b0010.
T32EE instruction set support. Defined values are:
| State3 | Meaning |
|---|---|
| 0b0000 |
Not implemented. |
| 0b0001 |
T32EE instruction set implemented. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
Jazelle extension support. Defined values are:
| State2 | Meaning |
|---|---|
| 0b0000 |
Not implemented. |
| 0b0001 |
Jazelle extension implemented, without clearing of JOSCR.CV on exception entry. |
| 0b0010 |
Jazelle extension implemented, with clearing of JOSCR.CV on exception entry. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
T32 instruction set support. Defined values are:
| State1 | Meaning |
|---|---|
| 0b0000 |
T32 instruction set not implemented. |
| 0b0001 | T32 encodings before the introduction of Thumb-2 technology implemented:
|
| 0b0011 |
T32 encodings after the introduction of Thumb-2 technology implemented, for all 16-bit and 32-bit T32 basic instructions. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0011.
A32 instruction set support. Defined values are:
| State0 | Meaning |
|---|---|
| 0b0000 |
A32 instruction set not implemented. |
| 0b0001 |
A32 instruction set implemented. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
Accesses to this register use the following encodings in the System register encoding space:
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0000 | 0b0001 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else R[t] = ID_PFR0; elsif PSTATE.EL == EL2 then R[t] = ID_PFR0; elsif PSTATE.EL == EL3 then R[t] = ID_PFR0;
04/07/2023 11:22; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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