PMINTENSET

Enables the generation of interrupt requests or, when FEAT_EBEP is implemented, PMU exceptions on overflows from the following counters:

Reading from this register shows which overflow interrupt requests or PMU exceptions are enabled.

Configuration

AArch32 System register PMINTENSET bits [31:0] are architecturally mapped to AArch64 System register PMINTENSET_EL1[31:0].

AArch32 System register PMINTENSET bits [31:0] are architecturally mapped to External register PMU.PMINTENSET_EL1[31:0].

This register is present only when EL1 is capable of using AArch32 and FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMINTENSET are UNDEFINED.

Attributes

Field descriptions

C, bit [31]

Interrupt request or PMU exception on unsigned overflow of PMCCNTR enable. On writes, allows software to enable the interrupt request or PMU exception on unsigned overflow of PMCCNTR. On reads, returns the interrupt request or PMU exception on unsigned overflow of PMCCNTR enable status.

C	Meaning
0b0	Interrupt request or PMU exception on unsigned overflow of PMCCNTR disabled.
0b1	Interrupt request or PMU exception on unsigned overflow of PMCCNTR enabled.

Access to this field is W1S.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

P<m>, bit [m], for m = 30 to 0

Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m> enable. On writes, allows software to enable the interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m>. On reads, returns the interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m> enable status.

P<m>	Meaning
0b0	Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m> disabled.
0b1	Interrupt request or PMU exception on unsigned overflow of PMEVCNTR<m> enabled.

Accessing this field has the following behavior:

This field reads-as-zero and ignores writes if any of the following are true:
- All of the following are true:
  - EL2 is implemented and enabled in the current Security state.
  - m >= UInt(MDCR_EL2.HPMN).
  - EL2 using AArch64.
  - Accessed at EL1.
- All of the following are true:
  - EL2 is implemented and enabled in the current Security state.
  - m >= UInt(HDCR.HPMN).
  - EL2 using AArch32.
  - Accessed at EL1.
- m >= UInt(PMCR.N).
Otherwise access to this field is W1S.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing PMINTENSET

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1001	0b1110	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMINTENSET; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMINTENSET; elsif PSTATE.EL == EL3 then R[t] = PMINTENSET;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1001	0b1110	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMINTENSET = R[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMINTENSET = R[t]; elsif PSTATE.EL == EL3 then PMINTENSET = R[t];

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

PMINTENSET, Performance Monitors Interrupt Enable Set register

Purpose