HDFGRTR2

Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and Statistical Profiling System registers.

Configuration

This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HDFGRTR2_EL2 are UNDEFINED.

Attributes

Field descriptions

Bits [63:23]

nTRBMPAM_EL1, bit [22]
When FEAT_TRBE_MPAM is implemented:

Trap MRS reads of TRBMPAM_EL1 at EL1 and EL0 using AArch64 to EL2.

nTRBMPAM_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads of TRBMPAM_EL1 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of TRBMPAM_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [21]

nTRCITECR_EL1, bit [20]
When FEAT_ITE is implemented:

Trap MRS reads of TRCITECR_EL1 at EL1 using AArch64 to EL2.

nTRCITECR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of TRCITECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of TRCITECR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMSDSFR_EL1, bit [19]
When FEAT_SPE_FDS is implemented:

Trap MRS reads of PMSDSFR_EL1 at EL1 using AArch64 to EL2.

nPMSDSFR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of PMSDSFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PMSDSFR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMDEVAFF_EL1, bit [18]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMDEVAFF_EL1 at EL1 using AArch64 to EL2.

nSPMDEVAFF_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of SPMDEVAFF_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SPMDEVAFF_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMID, bit [17]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMID	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of the specified System registers are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMSCR_EL1, bit [16]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMSCR_EL1 at EL1 using AArch64 to EL2.

nSPMSCR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of SPMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SPMSCR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMACCESSR_EL1, bit [15]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMACCESSR_EL1 at EL1 using AArch64 to EL2.

nSPMACCESSR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of SPMACCESSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SPMACCESSR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMCR_EL0, bit [14]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMCR_EL0 at EL1 and EL0 using AArch64 to EL2.

nSPMCR_EL0	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads of SPMCR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SPMCR_EL0 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMOVS, bit [13]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMOVS	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of the specified System registers are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMINTEN, bit [12]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMINTEN	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of the specified System registers are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMCNTEN, bit [11]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMCNTEN	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of the specified System registers are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMSELR_EL0, bit [10]
When FEAT_SPMU is implemented:

Trap MRS reads of SPMSELR_EL0 at EL1 and EL0 using AArch64 to EL2.

nSPMSELR_EL0	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads of SPMSELR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SPMSELR_EL0 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMEVTYPERn_EL0, bit [9]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2:

nSPMEVTYPERn_EL0	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of the specified System registers are not trapped by this mechanism.

Regardless of the value of this field, if event counter n is not implemented, a read of SPMEVTYPER<n>_EL0, SPMEVFILTR<n>_EL0, or SPMEVFILT2R<n>_EL0 is UNDEFINED.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSPMEVCNTRn_EL0, bit [8]
When FEAT_SPMU is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: SPMEVCNTR<n>_EL0.

nSPMEVCNTRn_EL0	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of the specified System registers are not trapped by this mechanism.

Regardless of the value of this field, if event counter n is not implemented, a read of SPMEVCNTR<n>_EL0 is UNDEFINED.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMSSCR_EL1, bit [7]
When FEAT_PMUv3_SS is implemented:

Trap MRS reads of PMSSCR_EL1 at EL1 using AArch64 to EL2.

nPMSSCR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of PMSSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PMSSCR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMSSDATA, bit [6]
When FEAT_PMUv3_SS is implemented:

Trap MRS reads of multiple System registers. Enables a trap on MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2:

PMCCNTSVR_EL1.
PMEVCNTSVR<n>_EL1.
PMICNTSVR_EL1, if FEAT_PMUv3_ICNTR is implemented.

nPMSSDATA	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of the specified System registers are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nMDSELR_EL1, bit [5]
When FEAT_Debugv8p9 is implemented:

Trap MRS reads of MDSELR_EL1 at EL1 using AArch64 to EL2.

nMDSELR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of MDSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of MDSELR_EL1 are not trapped by this mechanism.

It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMUACR_EL1, bit [4]
When FEAT_PMUv3p9 is implemented:

Trap MRS reads of PMUACR_EL1 at EL1 using AArch64 to EL2.

nPMUACR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of PMUACR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PMUACR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMICFILTR_EL0, bit [3]
When FEAT_PMUv3_ICNTR is implemented:

Trap MRS reads of PMICFILTR_EL0 at EL1 and EL0 using AArch64 to EL2.

nPMICFILTR_EL0	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then: MRS reads of PMICFILTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. PMCNTENCLR_EL0.F0, PMCNTENSET_EL0.F0, PMOVSCLR_EL0.F0, and PMOVSSET_EL0.F0 read as zero at EL1 and EL0. PMINTENCLR_EL1.F0 and PMINTENSET_EL1.F0 read as zero at EL1.
0b1	MRS reads of PMICFILTR_EL0 are not trapped by this mechanism.

nPMICFILTR_EL0

Meaning

0b0

If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then:

MRS reads of PMICFILTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
PMCNTENCLR_EL0.F0, PMCNTENSET_EL0.F0, PMOVSCLR_EL0.F0, and PMOVSSET_EL0.F0 read as zero at EL1 and EL0.
PMINTENCLR_EL1.F0 and PMINTENSET_EL1.F0 read as zero at EL1.

0b1

MRS reads of PMICFILTR_EL0 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMICNTR_EL0, bit [2]
When FEAT_PMUv3_ICNTR is implemented:

Trap MRS reads of PMICNTR_EL0 at EL1 and EL0 using AArch64 to EL2.

nPMICNTR_EL0	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, and HCR_EL2.{E2H, TGE} != {1, 1}, then MRS reads of PMICNTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PMICNTR_EL0 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMIAR_EL1, bit [1]
When FEAT_SEBEP is implemented:

Trap MRS reads of PMIAR_EL1 at EL1 using AArch64 to EL2.

nPMIAR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of PMIAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PMIAR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPMECR_EL1, bit [0]
When FEAT_EBEP is implemented or FEAT_PMUv3_SS is implemented:

Trap MRS reads of PMECR_EL1 at EL1 using AArch64 to EL2.

nPMECR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of PMECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PMECR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Accessing HDFGRTR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HDFGRTR2_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then X[t, 64] = NVMem[0x1A0]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HDFGRTR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HDFGRTR2_EL2;

MSR HDFGRTR2_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then NVMem[0x1A0] = X[t, 64]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HDFGRTR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HDFGRTR2_EL2 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0									nTRBMPAM_EL1	RES0	nTRCITECR_EL1	nPMSDSFR_EL1	nSPMDEVAFF_EL1	nSPMID	nSPMSCR_EL1	nSPMACCESSR_EL1	nSPMCR_EL0	nSPMOVS	nSPMINTEN	nSPMCNTEN	nSPMSELR_EL0	nSPMEVTYPERn_EL0	nSPMEVCNTRn_EL0	nPMSSCR_EL1	nPMSSDATA	nMDSELR_EL1	nPMUACR_EL1	nPMICFILTR_EL0	nPMICNTR_EL0	nPMIAR_EL1	nPMECR_EL1

HDFGRTR2_EL2, Hypervisor Debug Fine-Grained Read Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:23]

nTRBMPAM_EL1, bit [22]When FEAT_TRBE_MPAM is implemented:

Otherwise:

Bit [21]

nTRCITECR_EL1, bit [20]When FEAT_ITE is implemented:

Otherwise:

nPMSDSFR_EL1, bit [19]When FEAT_SPE_FDS is implemented:

Otherwise:

nSPMDEVAFF_EL1, bit [18]When FEAT_SPMU is implemented:

Otherwise:

nSPMID, bit [17]When FEAT_SPMU is implemented:

Otherwise:

nSPMSCR_EL1, bit [16]When FEAT_SPMU is implemented:

Otherwise:

nSPMACCESSR_EL1, bit [15]When FEAT_SPMU is implemented:

Otherwise:

nSPMCR_EL0, bit [14]When FEAT_SPMU is implemented:

Otherwise:

nSPMOVS, bit [13]When FEAT_SPMU is implemented:

Otherwise:

nSPMINTEN, bit [12]When FEAT_SPMU is implemented:

Otherwise:

nSPMCNTEN, bit [11]When FEAT_SPMU is implemented:

Otherwise:

nSPMSELR_EL0, bit [10]When FEAT_SPMU is implemented:

Otherwise:

nSPMEVTYPERn_EL0, bit [9]When FEAT_SPMU is implemented:

Otherwise:

nSPMEVCNTRn_EL0, bit [8]When FEAT_SPMU is implemented:

Otherwise:

nPMSSCR_EL1, bit [7]When FEAT_PMUv3_SS is implemented:

Otherwise:

nPMSSDATA, bit [6]When FEAT_PMUv3_SS is implemented:

Otherwise:

nMDSELR_EL1, bit [5]When FEAT_Debugv8p9 is implemented:

Otherwise:

nPMUACR_EL1, bit [4]When FEAT_PMUv3p9 is implemented:

Otherwise:

nPMICFILTR_EL0, bit [3]When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

nPMICNTR_EL0, bit [2]When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

nPMIAR_EL1, bit [1]When FEAT_SEBEP is implemented:

Otherwise:

nPMECR_EL1, bit [0]When FEAT_EBEP is implemented or FEAT_PMUv3_SS is implemented:

Otherwise:

Accessing HDFGRTR2_EL2

MRS <Xt>, HDFGRTR2_EL2

MSR HDFGRTR2_EL2, <Xt>

nTRBMPAM_EL1, bit [22]
When FEAT_TRBE_MPAM is implemented:

nTRCITECR_EL1, bit [20]
When FEAT_ITE is implemented:

nPMSDSFR_EL1, bit [19]
When FEAT_SPE_FDS is implemented:

nSPMDEVAFF_EL1, bit [18]
When FEAT_SPMU is implemented:

nSPMID, bit [17]
When FEAT_SPMU is implemented:

nSPMSCR_EL1, bit [16]
When FEAT_SPMU is implemented:

nSPMACCESSR_EL1, bit [15]
When FEAT_SPMU is implemented:

nSPMCR_EL0, bit [14]
When FEAT_SPMU is implemented:

nSPMOVS, bit [13]
When FEAT_SPMU is implemented:

nSPMINTEN, bit [12]
When FEAT_SPMU is implemented:

nSPMCNTEN, bit [11]
When FEAT_SPMU is implemented:

nSPMSELR_EL0, bit [10]
When FEAT_SPMU is implemented:

nSPMEVTYPERn_EL0, bit [9]
When FEAT_SPMU is implemented:

nSPMEVCNTRn_EL0, bit [8]
When FEAT_SPMU is implemented:

nPMSSCR_EL1, bit [7]
When FEAT_PMUv3_SS is implemented:

nPMSSDATA, bit [6]
When FEAT_PMUv3_SS is implemented:

nMDSELR_EL1, bit [5]
When FEAT_Debugv8p9 is implemented:

nPMUACR_EL1, bit [4]
When FEAT_PMUv3p9 is implemented:

nPMICFILTR_EL0, bit [3]
When FEAT_PMUv3_ICNTR is implemented:

nPMICNTR_EL0, bit [2]
When FEAT_PMUv3_ICNTR is implemented:

nPMIAR_EL1, bit [1]
When FEAT_SEBEP is implemented:

nPMECR_EL1, bit [0]
When FEAT_EBEP is implemented or FEAT_PMUv3_SS is implemented: