The ID_AA64MMFR4_EL1 characteristics are:
Provides additional information about implemented memory model and memory management support in AArch64.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_AA64MMFR4_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | EIESB | RES0 | |||||||||||||||||||||||||||||
Reserved, RES0.
Early Implicit Error Synchronization event. Indicates whether the implicit Error synchronization event inserted on taking an exception to ELx when SCTLR_ELx.IESB is 1 is inserted before or after the exception is taken. Defined values are:
| EIESB | Meaning |
|---|---|
| 0b1111 |
An implicit Error synchronization event is always inserted after an exception is taken. |
| 0b0000 |
Behavior is not described. |
| 0b0001 |
When SError exceptions are routed to EL3, and either FEAT_DoubleFault is not implemented or the Effective value of SCR_EL3.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to EL3. |
| 0b0010 |
When SError exceptions are routed to ELx, and either FEAT_DoubleFault2 is not implemented or the Effective value of the applicable one of SCR_EL3.NMEA or SCTLR2_ELx.NMEA is 1, an implicit Error synchronization event is inserted before an exception taken to ELx. |
All other values are reserved.
This field describes the PE behavior on taking an exception to ELx when SCTLR_ELx.IESB is 1. This field does not apply when SCTLR_ELx.IESB is 0.
Inserting the event before the exception is taken means that if the Error synchronization event causes an SError exception to become pending, and SError exceptions are not masked and not disabled, then the SError exception is taken in place of the original exception.
Reserved, RES0.
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0111 | 0b100 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64MMFR4_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64MMFR4_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64MMFR4_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64MMFR4_EL1;
04/07/2023 11:23; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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