SCTLR2

When FEAT_VHE is implemented and the value of HCR_EL2.{E2H,TGE} is {1,1}, these controls also apply to execution at EL0.

Configuration

This register is present only when FEAT_SCTLR2 is implemented. Otherwise, direct accesses to SCTLR2_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

Bits [63:7]

EnIDCP128, bit [6]
When FEAT_SYSREG128 is implemented:

Enables access to IMPLEMENTATION DEFINED 128-bit System registers.

EnIDCP128	Meaning
0b0	Accesses at EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL2 using an ESR_EL2.EC value of 0x14, unless the access generates a higher priority exception. Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL2.
0b1	No accesses are trapped by this control.

EnIDCP128

Meaning

0b0

Accesses at EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL2 using an ESR_EL2.EC value of 0x14, unless the access generates a higher priority exception.

Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL2.

0b1

No accesses are trapped by this control.

This field is ignored by the PE and treated as zero when SCR_EL3.SCTLR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EASE, bit [5]
When FEAT_DoubleFault2 is implemented:

EASE	Meaning
0b0	Synchronous External abort exceptions taken to EL2 are taken to the appropriate synchronous exception vector offset from VBAR_EL2.
0b1	Synchronous External abort exceptions taken to EL2 are taken to the appropriate SError exception vector offset from VBAR_EL2.

Otherwise:

EnANERR, bit [4]
When FEAT_ANERR is implemented:

Enable Asynchronous Normal Read Error.

EnANERR	Meaning
0b0	External abort on Normal memory reads generate synchronous Data Abort exceptions in the EL2 and EL2&0 translation regimes.
0b1	External abort on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL2 and EL2&0 translation regimes.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

SVE register loads, when FEAT_SME is implemented and the PE is in Streaming SVE mode.
SME register loads.
LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
LD64B and ST64BV{0} instructions that return a value to the PE.
RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Normal memory reads.

This field is ignored by the PE and treated as zero when SCR_EL3.SCTLR2En == 0.

Otherwise, this field is ignored by the PE and treated as one when all of the following are true:

FEAT_ADERR is implemented.
ID_AA64MMFR3_EL1.ANERR reads as 0b0010.
SCTLR2_EL2.EnADERR is 1.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

Enable Asynchronous Device Read Error.

EnADERR	Meaning
0b0	External abort on Device memory reads generate synchronous Data Abort exceptions in the EL2 and EL2&0 translation regimes.
0b1	External abort on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL2 and EL2&0 translation regimes.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

SIMD&FP register loads.
SVE register loads.
SME register loads.
LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
LD64B and ST64BV{0} instructions that return a value to the PE.
RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Device memory reads.

This field is ignored by the PE and treated as zero when SCR_EL3.SCTLR2En == 0.

Otherwise, this field is ignored by the PE and treated as one when all of the following are true:

FEAT_ANERR is implemented.
ID_AA64MMFR3_EL1.ADERR reads as 0b0010.
SCTLR2_EL2.EnANERR is 1.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

NMEA, bit [2]
When FEAT_DoubleFault2 is implemented:

NMEA	Meaning
0b0	SError exceptions are not taken at EL2 if PSTATE.A == 1, unless routed to a higher Exception level.
0b1	SError exceptions are taken at EL2 regardless of the value of PSTATE.A, unless routed to a higher Exception level.

Otherwise:

EMEC, bit [1]
When FEAT_MEC is implemented:

EMEC	Meaning
0b0	MEC is not enabled for the Realm physical address space.
0b1	MEC is enabled for the Realm physical address space.

Otherwise:

Bit [0]

Accessing SCTLR2_EL2

When FEAT_VHE is implemented, and HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the register name SCTLR2_EL2 or SCTLR2_EL1 are not guaranteed to be ordered with respect to accesses using the other register name.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLR2_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = SCTLR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLR2_EL2;

MSR SCTLR2_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then SCTLR2_EL2 = X[t, 64];

MRS <Xt>, SCTLR2_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.SCTLR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SCTLR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then X[t, 64] = NVMem[0x278]; else X[t, 64] = SCTLR2_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then X[t, 64] = SCTLR2_EL2; else X[t, 64] = SCTLR2_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLR2_EL1;

MSR SCTLR2_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.SCTLR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.SCTLR2En == '0') then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x278] = X[t, 64]; else SCTLR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.SCTLR2En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.SCTLR2En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then SCTLR2_EL2 = X[t, 64]; else SCTLR2_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then SCTLR2_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																									EnIDCP128	EASE	EnANERR	EnADERR	NMEA	EMEC	RES0

SCTLR2_EL2, System Control Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:7]

EnIDCP128, bit [6]
When FEAT_SYSREG128 is implemented:

Otherwise:

EASE, bit [5]
When FEAT_DoubleFault2 is implemented:

Otherwise:

EnANERR, bit [4]
When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

Otherwise:

NMEA, bit [2]
When FEAT_DoubleFault2 is implemented:

Otherwise:

EMEC, bit [1]
When FEAT_MEC is implemented:

Otherwise:

Bit [0]

Accessing SCTLR2_EL2

MRS <Xt>, SCTLR2_EL2

MSR SCTLR2_EL2, <Xt>

MRS <Xt>, SCTLR2_EL1

MSR SCTLR2_EL1, <Xt>

SCTLR2_EL2, System Control Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:7]

EnIDCP128, bit [6]When FEAT_SYSREG128 is implemented:

Otherwise:

EASE, bit [5]When FEAT_DoubleFault2 is implemented:

Otherwise:

EnANERR, bit [4]When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]When FEAT_ADERR is implemented:

Otherwise:

NMEA, bit [2]When FEAT_DoubleFault2 is implemented:

Otherwise:

EMEC, bit [1]When FEAT_MEC is implemented:

Otherwise:

Bit [0]

Accessing SCTLR2_EL2

MRS <Xt>, SCTLR2_EL2

MSR SCTLR2_EL2, <Xt>

MRS <Xt>, SCTLR2_EL1

MSR SCTLR2_EL1, <Xt>

EnIDCP128, bit [6]
When FEAT_SYSREG128 is implemented:

EASE, bit [5]
When FEAT_DoubleFault2 is implemented:

EnANERR, bit [4]
When FEAT_ANERR is implemented:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

NMEA, bit [2]
When FEAT_DoubleFault2 is implemented:

EMEC, bit [1]
When FEAT_MEC is implemented: