SCTLR2

This register is present only when FEAT_SCTLR2 is implemented. Otherwise, direct accesses to SCTLR2_EL3 are UNDEFINED.

Attributes

Field descriptions

Bits [63:5]

EnANERR, bit [4]
When FEAT_ANERR is implemented:

Enable Asynchronous Normal Read Error.

EnANERR	Meaning
0b0	External abort on Normal memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.
0b1	External abort on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

SVE register loads, when FEAT_SME is implemented and the PE is in Streaming SVE mode.
SME register loads.
LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
LD64B and ST64BV{0} instructions that return a value to the PE.
RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Normal memory reads.

This field is ignored by the PE and treated as one when all of the following are true:

FEAT_ADERR is implemented.
ID_AA64MMFR3_EL1.ANERR reads as 0b0010.
SCTLR2_EL3.EnADERR is 1.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Otherwise:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

Enable Asynchronous Device Read Error.

EnADERR	Meaning
0b0	External abort on Device memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.
0b1	External abort on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

SIMD&FP register loads.
SVE register loads.
SME register loads.
LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
LD64B and ST64BV{0} instructions that return a value to the PE.
RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

Setting this field to 0 might have a performance impact for Device memory reads.

This field is ignored by the PE and treated as one when all of the following are true:

FEAT_ANERR is implemented.
ID_AA64MMFR3_EL1.ADERR reads as 0b0010.
SCTLR2_EL3.EnANERR is 1.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Otherwise:

Bit [2]

EMEC, bit [1]
When FEAT_MEC is implemented:

Enables MEC. When enabled, memory accesses to the Realm physical address space are associated with MECID_RL_A_EL3.

EMEC	Meaning
0b0	MEC is not enabled for the Realm physical address space.
0b1	MEC is enabled for the Realm physical address space.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Otherwise:

Bit [0]

Accessing SCTLR2_EL3

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SCTLR2_EL3

op0	op1	CRn	CRm	op2
0b11	0b110	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLR2_EL3;

MSR SCTLR2_EL3, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b110	0b0001	0b0000	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then SCTLR2_EL3 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																											EnANERR	EnADERR	RES0	EMEC	RES0

SCTLR2_EL3, System Control Register (EL3)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:5]

EnANERR, bit [4]
When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

Otherwise:

Bit [2]

EMEC, bit [1]
When FEAT_MEC is implemented:

Otherwise:

Bit [0]

Accessing SCTLR2_EL3

MRS <Xt>, SCTLR2_EL3

MSR SCTLR2_EL3, <Xt>

SCTLR2_EL3, System Control Register (EL3)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:5]

EnANERR, bit [4]When FEAT_ANERR is implemented:

Otherwise:

EnADERR, bit [3]When FEAT_ADERR is implemented:

Otherwise:

Bit [2]

EMEC, bit [1]When FEAT_MEC is implemented:

Otherwise:

Bit [0]

Accessing SCTLR2_EL3

MRS <Xt>, SCTLR2_EL3

MSR SCTLR2_EL3, <Xt>

EnANERR, bit [4]
When FEAT_ANERR is implemented:

EnADERR, bit [3]
When FEAT_ADERR is implemented:

EMEC, bit [1]
When FEAT_MEC is implemented: