TPIDR_EL0

Provides a location where software executing at EL0 can store thread identifying information, for OS management purposes.

Configuration

AArch64 System register TPIDR_EL0 bits [31:0] are architecturally mapped to AArch32 System register TPIDRURW[31:0].

Attributes

Field descriptions

Bits [63:0]

Accessing TPIDR_EL0

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TPIDR_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1101	0b0000	0b010

if PSTATE.EL == EL0 then if EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = TPIDR_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = TPIDR_EL0; elsif PSTATE.EL == EL2 then X[t, 64] = TPIDR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = TPIDR_EL0;

MSR TPIDR_EL0, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b1101	0b0000	0b010

if PSTATE.EL == EL0 then if EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TPIDR_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TPIDR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else TPIDR_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then TPIDR_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then TPIDR_EL0 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Thread ID
Thread ID

TPIDR_EL0, EL0 Read/Write Software Thread ID Register