The TRCITECR_EL2 characteristics are:
Provides EL2 controls for Trace Instrumentation.
This register is present only when FEAT_ITE is implemented and System register access to the trace unit registers is implemented. Otherwise, direct accesses to TRCITECR_EL2 are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
TRCITECR_EL2 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | E2E | E0HE | |||||||||||||||||||||||||||||
Reserved, RES0.
EL2 Instrumentation Trace Enable.
| E2E | Meaning |
|---|---|
| 0b0 |
Instrumentation trace prohibited at EL2. |
| 0b1 |
Instrumentation trace not prohibited at EL2. |
The reset behavior of this field is:
EL0 Instrumentation Trace Enable.
| E0HE | Meaning |
|---|---|
| 0b0 |
Instrumentation trace prohibited at EL0 when HCR_EL2.TGE == 1. |
| 0b1 |
Instrumentation trace not prohibited at EL0 when HCR_EL2.TGE == 1. |
This field is ignored by the PE when any of the following are true:
The reset behavior of this field is:
When FEAT_VHE is implemented, and HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL2 using the register name TRCITECR_EL2 or TRCITECR_EL1 are not guaranteed to be ordered with respect to accesses using the other register name.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0001 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnITE == '0' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnITE == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = TRCITECR_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = TRCITECR_EL2;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0001 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnITE == '0' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnITE == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else TRCITECR_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then TRCITECR_EL2 = X[t, 64];
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0001 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnITE == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && HDFGRTR2_EL2.nTRCITECR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnITE == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then X[t, 64] = NVMem[0x888]; else X[t, 64] = TRCITECR_EL1; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnITE == '0' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnITE == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then X[t, 64] = TRCITECR_EL2; else X[t, 64] = TRCITECR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = TRCITECR_EL1;
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0001 | 0b0010 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnITE == '0' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && HDFGWTR2_EL2.nTRCITECR_EL1 == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.EnITE == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x888] = X[t, 64]; else TRCITECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.EnITE == '0' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.EnITE == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif HCR_EL2.E2H == '1' then TRCITECR_EL2 = X[t, 64]; else TRCITECR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then TRCITECR_EL1 = X[t, 64];
04/07/2023 11:26; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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