The AMDEVARCH characteristics are:
Identifies the programmers' model architecture of the AMU component.
It is IMPLEMENTATION DEFINED whether AMDEVARCH is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented and an implementation implements AMDEVARCH. Otherwise, direct accesses to AMDEVARCH are RES0.
AMDEVARCH is a 32-bit register.
This register is part of the AMU block.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ARCHITECT | PRESENT | REVISION | ARCHID | ||||||||||||||||||||||||||||
Defines the architecture of the component. For AMU, this is Arm Limited.
Bits [31:28] are the JEP106 continuation code, 0x4.
Bits [27:21] are the JEP106 ID code, 0x3B.
Reads as 0b01000111011.
Access to this field is RO.
Indicates that the DEVARCH is present.
Reads as 0b1.
Access to this field is RO.
Defines the architecture revision. For architectures defined by Arm this is the minor revision.
| REVISION | Meaning |
|---|---|
| 0b0000 |
Architecture revision is AMUv1. |
All other values are reserved.
Access to this field is RO.
Defines this part to be an AMU component. For architectures defined by Arm this is further subdivided.
For AMU:
AMDEVARCH.ARCHVER = 0x0, which corresponds to AMU architecture version AMUv1.
If FEAT_AMU_EXT32 is implemented, AMDEVARCH is 0xA66.
If FEAT_AMU_EXT64 is implemented, AMDEVARCH is 0xA67.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| ARCHID | Meaning |
|---|---|
| 0x0A66 |
AMUv1, with FEAT_AMU_EXT32 implemented. |
| 0x0A67 |
AMUv1, with FEAT_AMU_EXT64 implemented. |
Access to this field is RO.
Accesses to this register use the following encodings:
Accesses on this interface are RO.
Accesses on this interface are RO.
04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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