The CNTSR characteristics are:
Provides counter frequency status information.
It is IMPLEMENTATION DEFINED whether CNTSR is implemented in the Core power domain or in the Debug power domain.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTSR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | FCACK | RES0 | DBGH | RES0 |
Reserved, RES0.
Frequency Change Acknowledge. Indicates the currently selected entry in the Frequency modes table, see 'The Frequency modes table'.
The reset behavior of this field is:
Reserved, RES0.
Indicates whether the counter is halted because the Halt-on-debug signal is asserted:
DBGH | Meaning |
---|---|
0b0 |
Counter is not halted. |
0b1 |
Counter is halted. |
The reset behavior of this field is:
Reserved, RES0.
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.
Component | Frame | Offset | Instance |
---|---|---|---|
Timer | CNTControlBase | 0x004 | CNTSR |
Accesses on this interface are RO.
04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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