The CTILSR characteristics are:
Indicates the current status of the Software Lock for CTI registers.
The optional Software Lock provides a lock to prevent memory-mapped writes to the Cross-Trigger Interface registers. Use of this lock mechanism reduces the risk of accidental damage to the contents of the Cross-Trigger Interface registers. It does not, and cannot, prevent all accidental or malicious damage.
CTILSR is in the Debug power domain.
If FEAT_Debugv8p4 is implemented, the Software Lock is not implemented.
Software uses CTILAR to set or clear the lock, and CTILSR to check the current status of the lock.
CTILSR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | nTT | SLK | SLI |
Reserved, RES0.
Not thirty-two bit access required. RAZ.
Software Lock status for this component. For an access to LSR that is not a memory-mapped access, or when the Software Lock is not implemented, this field is RES0.
For memory-mapped accesses when the Software Lock is implemented, possible values of this field are:
SLK | Meaning |
---|---|
0b0 |
Lock clear. Writes are permitted to this component's registers. |
0b1 |
Lock set. Writes to this component's registers are ignored, and reads have no side effects. |
The reset behavior of this field is:
Reserved, RAZ.
Software Lock implemented. For an access to LSR that is not a memory-mapped access, this field is RAZ. For memory-mapped accesses, the value of this field is IMPLEMENTATION DEFINED. Permitted values are:
SLI | Meaning |
---|---|
0b0 |
Software Lock not implemented or not memory-mapped access. |
0b1 |
Software Lock implemented and memory-mapped access. |
Component | Offset | Instance |
---|---|---|
CTI | 0xFB4 | CTILSR |
Accesses on this interface are RO.
04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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