The CTIPIDR4 characteristics are:
Provides information to identify a CTI component.
For more information, see 'About the Peripheral identification scheme'.
CTIPIDR4 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
CTIPIDR4 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | SIZE | DES_2 | |||||||||||||||||||||||||||||
Reserved, RES0.
Size of the component. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.
Reads as 0b0000.
Access to this field is RO.
Designer, JEP106 continuation code, least significant nibble. For Arm Limited, this field is 0b0100.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
| Component | Offset | Instance |
|---|---|---|
| CTI | 0xFD0 | CTIPIDR4 |
Accesses on this interface are RO.
04/07/2023 11:26; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.