EDAA32PFR, External Debug Auxiliary Processor Feature Register

The EDAA32PFR characteristics are:

Purpose

Provides information about implemented PE features.

Note

The register mnemonic, EDAA32PFR, is derived from previous definitions of this register that defined this register only when AArch64 was not supported.

For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.

Configuration

There are no configuration notes.

Attributes

EDAA32PFR is a 64-bit register.

Field descriptions

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0												MSA_frac				EL3				EL2				PMSA				VMSA

Bits [63:20]

Reserved, RES0.

MSA_frac, bits [19:16]
When EDAA32PFR.PMSA == 0b0000 and EDAA32PFR.VMSA == 0b1111:

Memory System Architecture fractional field. This holds the information on additional Memory System Architectures supported. Defined values are:

MSA_frac	Meaning
0b0001	PMSAv8-64 supported in all translation regimes. VMSAv8-64 not supported.
0b0010	PMSAv8-64 supported in all translation regimes. In addition to PMSAv8-64, stage 1 EL1&0 translation regime also supports VMSAv8-64.

All other values are reserved.

Otherwise:

Reserved, RES0.

EL3, bits [15:12]
When EDPFR.EL3 == 0b0000:

AArch32 EL3 Exception level handling. Defined values are:

EL3	Meaning
0b0000	EL3 is not implemented or can be executed in AArch64 state.
0b0001	EL3 can be executed in AArch32 state only.

All other values are reserved.

Note

EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state.

Otherwise:

Reserved, RAZ.

EL2, bits [11:8]
When EDPFR.EL2 == 0b0000:

AArch32 EL2 Exception level handling. Defined values are:

EL2	Meaning
0b0000	EL2 is not implemented or can be executed in AArch64 state.
0b0001	EL2 can be executed in AArch32 state only.

All other values are reserved.

Note

EDPFR.{EL1, EL0} indicate whether EL1 and EL0 can only be executed in AArch32 state.

Otherwise:

Reserved, RAZ.

PMSA, bits [7:4]

Indicates support for a 32-bit PMSA. Defined values are:

PMSA	Meaning
0b0000	PMSA-32 not supported.
0b0100	PMSAv8-32 supported.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

VMSA, bits [3:0]
When EDAA32PFR.PMSA != 0b0000:

Indicates support for a VMSA in addition to a 32-bit PMSA Defined values are:

VMSA	Meaning
0b0000	VMSA not supported.

All other values are reserved.

When EDAA32PFR.PMSA == 0b0000:

Defined values are:

VMSA	Meaning
0b0000	VMSAv8-64 supported.
0b1111	Memory system architecture described by EDAA32PFR.MSA_frac.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

Otherwise:

Reserved, RAZ.

Accessing EDAA32PFR

EDAA32PFR can be accessed through the external debug interface:

Component	Offset	Instance
Debug	0xD60	EDAA32PFR

This interface is accessible as follows:

When IsCorePowered() and !DoubleLockStatus(), accesses to this register are RO.
When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are IMPDEF.

04/07/2023 11:26; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68

EDAA32PFR, External Debug Auxiliary Processor Feature Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:20]

MSA_frac, bits [19:16]When EDAA32PFR.PMSA == 0b0000 and EDAA32PFR.VMSA == 0b1111:

Otherwise:

EL3, bits [15:12]When EDPFR.EL3 == 0b0000:

Otherwise:

EL2, bits [11:8]When EDPFR.EL2 == 0b0000:

Otherwise:

PMSA, bits [7:4]

VMSA, bits [3:0]When EDAA32PFR.PMSA != 0b0000:

When EDAA32PFR.PMSA == 0b0000:

Otherwise:

Accessing EDAA32PFR

EDAA32PFR can be accessed through the external debug interface:

MSA_frac, bits [19:16]
When EDAA32PFR.PMSA == 0b0000 and EDAA32PFR.VMSA == 0b1111:

EL3, bits [15:12]
When EDPFR.EL3 == 0b0000:

EL2, bits [11:8]
When EDPFR.EL2 == 0b0000:

VMSA, bits [3:0]
When EDAA32PFR.PMSA != 0b0000: