The EDCIDR3 characteristics are:
Provides information to identify an external debug component.
For more information, see 'About the Component Identification scheme'.
When FEAT_DoPD is implemented, EDCIDR3 is in the Core power domain. Otherwise, EDCIDR3 is in the Debug power domain.
Implementation of this register is OPTIONAL.
This register is required for CoreSight compliance.
EDCIDR3 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | PRMBL_3 |
Reserved, RES0.
Preamble.
Reads as 0xB1.
Access to this field is RO.
Component | Offset | Instance |
---|---|---|
Debug | 0xFFC | EDCIDR3 |
This interface is accessible as follows:
04/07/2023 11:22; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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