EDESR, External Debug Event Status Register

The EDESR characteristics are:

Purpose

Indicates the status of internally pending Halting debug events.

Configuration

EDESR is in the Core power domain.

Attributes

EDESR is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																												EC	SS	RC	OSUC

Bits [31:4]

Reserved, RES0.

EC, bit [3]
When FEAT_Debugv8p8 is implemented:

Exception Catch debug event pending.

EC	Meaning
0b0	Exception Catch debug event is not pending.
0b1	Exception Catch debug event is pending.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Access to this field is W1C.

Otherwise:

Reserved, RES0.

SS, bit [2]
When FEAT_DoPD is implemented:

Halting step debug event pending. Possible values of this field are:

SS	Meaning
0b0	Reading this means that a Halting step debug event is not pending. Writing this means no action.
0b1	Reading this means that a Halting step debug event is pending. Writing this clears the pending Halting step debug event.

The reset behavior of this field is:

On a Cold reset, this field resets to 0.

Otherwise:

Halting step debug event pending. Possible values of this field are:

SS	Meaning
0b0	Reading this means that a Halting step debug event is not pending. Writing this means no action.
0b1	Reading this means that a Halting step debug event is pending. Writing this clears the pending Halting step debug event.

The reset behavior of this field is:

On a Warm reset, this field resets to the value in EDECR.SS.

RC, bit [1]

Reset Catch debug event pending. Possible values of this field are:

RC	Meaning
0b0	Reading this means that a Reset Catch debug event is not pending. Writing this means no action.
0b1	Reading this means that a Reset Catch debug event is pending. Writing this clears the pending Reset Catch debug event.

The reset behavior of this field is:

On a Warm reset:
- When FEAT_DoPD is implemented, this field resets to the value in CTIDEVCTL.RCE.
- When FEAT_DoPD is not implemented, this field resets to the value in EDECR.RCE.

OSUC, bit [0]

OS Unlock Catch debug event pending. Possible values of this field are:

OSUC	Meaning
0b0	Reading this means that an OS Unlock Catch debug event is not pending. Writing this means no action.
0b1	Reading this means that an OS Unlock Catch debug event is pending. Writing this clears the pending OS Unlock Catch debug event.

The reset behavior of this field is:

On a Warm reset, this field resets to 0.

Accessing EDESR

If a request to clear a pending Halting debug event is received at or about the time when halting becomes allowed, it is CONSTRAINED UNPREDICTABLE whether the event is taken.

If Core power is removed while a Halting debug event is pending, it is lost. However, it might become pending again when the Core is powered back on and Cold reset.

EDESR can be accessed through the external debug interface:

Component	Offset	Instance
Debug	0x020	EDESR

This interface is accessible as follows:

When IsCorePowered(), !DoubleLockStatus() and SoftwareLockStatus(), accesses to this register are RO.
When IsCorePowered(), !DoubleLockStatus() and !SoftwareLockStatus(), accesses to this register are RW.
Otherwise, accesses to this register generate an error response.

04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68

EDESR, External Debug Event Status Register

Purpose

Configuration

Attributes

Field descriptions

Bits [31:4]

EC, bit [3]When FEAT_Debugv8p8 is implemented:

Otherwise:

SS, bit [2]When FEAT_DoPD is implemented:

Otherwise:

RC, bit [1]

OSUC, bit [0]

Accessing EDESR

EDESR can be accessed through the external debug interface:

EC, bit [3]
When FEAT_Debugv8p8 is implemented:

SS, bit [2]
When FEAT_DoPD is implemented: