The ERRCRICR0 characteristics are:
Critical Error Interrupt configuration register.
This register is present only when (the Critical Error Interrupt is implemented or the implementation does not use the recommended layout for the ERRIRQCR registers) and interrupt configuration registers are implemented. Otherwise, direct accesses to ERRCRICR0 are RES0.
ERRCRICR0 is implemented only as part of a memory-mapped group of error records.
ERRCRICR0 is a 64-bit register.
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RES0 | |||||||||||||||||||||||||||||||
RES0 |
Reserved, RES0.
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RES0 | ADDR | ||||||||||||||||||||||||||||||
ADDR | RES0 |
Reserved, RES0.
Message Signaled Interrupt address. (ERRCRICR0.ADDR << 2) is the address that the component writes to when signaling the Critical Error Interrupt. Bits [1:0] of the address are always zero.
The physical address size supported by the component is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.
The reset behavior of this field is:
Reserved, RES0.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED |
IMPLEMENTATION DEFINED.
If the implementation does not use the recommended layout for the ERRIRQCR registers then accesses to ERRCRICR0 are IMPLEMENTATION DEFINED.
Component | Offset | Instance |
---|---|---|
RAS | 0xEA0 | ERRCRICR0 |
This interface is accessible as follows:
04/07/2023 11:27; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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