The GICC_IIDR characteristics are:
Provides information about the implementer and revision of the CPU interface.
This register is present only when FEAT_GICv3_LEGACY is implemented. Otherwise, direct accesses to GICC_IIDR are RES0.
GICC_IIDR is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ProductID | Architecture_version | Revision | Implementer |
Product Identifier.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
The version of the GIC architecture that is implemented.
Architecture_version | Meaning |
---|---|
0b0001 |
GICv1. |
0b0010 |
GICv2. |
0b0011 |
FEAT_GICv3 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
0b0100 |
FEAT_GICv4 memory-mapped interface supported. Support for the System register interface is discoverable from PE registers ID_PFR1 and ID_AA64PFR0_EL1. |
Other values are reserved.
Revision number for the CPU interface.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
Contains the JEP106 code of the company that implemented the CPU interface.
Component | Offset | Instance |
---|---|---|
GIC CPU interface | 0x00FC | GICC_IIDR |
This interface is accessible as follows:
04/07/2023 11:26; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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