GICD_ICPENDR<n>E, Interrupt Clear-Pending Registers (extended SPI range), n = 0 - 31

The GICD_ICPENDR<n>E characteristics are:

Purpose

Removes the pending state to the corresponding SPI in the extended SPI range.

This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_ICPENDR<n>E are RES0.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1, the number of implemented GICD_ICPENDR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.

GICD_ICPENDR<n>E is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Clear_pending_bit31	Clear_pending_bit30	Clear_pending_bit29	Clear_pending_bit28	Clear_pending_bit27	Clear_pending_bit26	Clear_pending_bit25	Clear_pending_bit24	Clear_pending_bit23	Clear_pending_bit22	Clear_pending_bit21	Clear_pending_bit20	Clear_pending_bit19	Clear_pending_bit18	Clear_pending_bit17	Clear_pending_bit16	Clear_pending_bit15	Clear_pending_bit14	Clear_pending_bit13	Clear_pending_bit12	Clear_pending_bit11	Clear_pending_bit10	Clear_pending_bit9	Clear_pending_bit8	Clear_pending_bit7	Clear_pending_bit6	Clear_pending_bit5	Clear_pending_bit4	Clear_pending_bit3	Clear_pending_bit2	Clear_pending_bit1	Clear_pending_bit0

For the extended PPIs, removes the pending state to interrupt number x. Reads and writes have the following behavior:

Clear_pending_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not pending. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is pending, or active and pending. If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases: If the interrupt is not pending and is not active and pending. If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICD_ISPENDR<n>E. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending.

Clear_pending_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not pending.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending.

If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active.

This has no effect in the following cases:

If the interrupt is not pending and is not active and pending.
If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICD_ISPENDR<n>E. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending.

The reset behavior of this field is:

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_ICPENDR<n>E number, n, is given by n = (m-4096) DIV 32.
The offset of the required GICD_ICPENDR<n>E is (0x1800 + (4*n)).
The bit number of the required group modifier bit in this register is (m-4096) MOD 32.

When affinity routing is not enabled for the Security state of an interrupt in GICD_ICPENDR<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

Component	Frame	Offset	Instance
GIC Distributor	Dist_base	0x1800 + (4 * n)	GICD_ICPENDR<n>E

Accesses on this interface are RW.

04/07/2023 11:25; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68