GICD_IROUTER<n>E

When affinity routing is enabled, provides routing information for the corresponding SPI in the extended SPI range.

Configuration

This register is present only when FEAT_GICv3p1 is implemented. Otherwise, direct accesses to GICD_IROUTER<n>E are RES0.

When GICD_TYPER.ESPI==1, the number of implemented GICD_IROUTER<n>E registers is (((GICD_TYPER.ESPI_range+1)*32)-1). Registers are numbered from 0.

Attributes

Field descriptions

Bits [63:40]

Aff3, bits [39:32]

Affinity level 3.

The reset behavior of this field is:

On a GIC reset, this field resets to an architecturally UNKNOWN value.

Interrupt_Routing_Mode, bit [31]

Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy:

Interrupt_Routing_Mode	Meaning
0b0	Interrupts routed to the PE specified by a.b.c.d. In this routing, a, b, c, and d are the values of fields Aff3, Aff2, Aff1, and Aff0 respectively.
0b1	Interrupts routed to any PE defined as a participating node.

If GICD_IROUTER<n>E.IRM == 0 and the affinity path does not correspond to an implemented PE, then if the corresponding interrupt becomes pending behavior is CONSTRAINED UNPREDICTABLE:

The interrupt is not forwarded to any PE, direct reads return the written value
The affinity path is treated as an UNKNOWN implemented PE, direct reads return the UNKNOWN implemented PE
The affinity path is treated as an UNKNOWN implemented PE, direct reads return the written value

When GICD_TYPER.No1N is 1, 1 of N distribution is not supported. Setting this field to 1 is CONSTRAINED UNPREDICTABLE, the permitted behaviors are:

The field behaves as if set to 0 for all purposes.
The field behaves as if set to 0 for all purposes other than a direct-read of the register.
The interrupt is treated as not targeting any PE.

When this bit is set to 1, GICD_IROUTER<n>E.{Aff3, Aff2, Aff1, Aff0} are UNKNOWN.

Note

An implementation might choose to make the Aff<n> fields RO when this field is 1.

The reset behavior of this field is:

On a GIC reset, this field resets to an architecturally UNKNOWN value.

Bits [30:24]

Aff2, bits [23:16]

Affinity level 2.

The reset behavior of this field is:

On a GIC reset, this field resets to an architecturally UNKNOWN value.

Aff1, bits [15:8]

Affinity level 1.

The reset behavior of this field is:

On a GIC reset, this field resets to an architecturally UNKNOWN value.

Aff0, bits [7:0]

Affinity level 0.

The reset behavior of this field is:

On a GIC reset, this field resets to an architecturally UNKNOWN value.

Accessing GICD_IROUTER<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICD_IROUTER<n>E, the register is RES0.

When GICD_CTLR.DS==0, a register that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses.

GICD_IROUTER<n>E can be accessed through the memory-mapped interfaces:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								Aff3
Interrupt_Routing_Mode	RES0							Aff2								Aff1								Aff0

GICD_IROUTER<n>E, Interrupt Routing Registers (Extended SPI Range), n = 0 - 1023

Purpose

Configuration

Attributes

Field descriptions

Bits [63:40]

Aff3, bits [39:32]

Interrupt_Routing_Mode, bit [31]

Bits [30:24]

Aff2, bits [23:16]

Aff1, bits [15:8]

Aff0, bits [7:0]

Accessing GICD_IROUTER<n>E

GICD_IROUTER<n>E can be accessed through the memory-mapped interfaces: