The GICM_TYPER characteristics are:
Provides information about what features the GIC implementation supports.
This register is available in all configurations of the GIC. When GICD_CTLR.DS==0, this register is Common.
GICM_TYPER is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Valid | CLR | SR | INTID | RES0 | NumSPIs |
Reports whether GICM_TYPER content is valid.
Valid | Meaning |
---|---|
0b0 |
GICM_TYPER reports no information on the capabilities of the GICM frame, all other fields are RES0. |
0b1 |
GICM_TYPER reports information on capabilities of GICM frame. |
Reports whether MSI clear registers are supported.
CLR | Meaning |
---|---|
0b0 |
MSI clear registers not implemented. |
0b1 |
MSI clear registers implemented. |
Reports whether Secure aliases of MSI registers are supported.
SR | Meaning |
---|---|
0b0 |
Secure aliases of MSI registers not implemented. |
0b1 |
Secure aliases of MSI registers implemented. |
INTID of the first SPI assigned to this GICM frame.
Reserved, RES0.
Number of SPIs assigned to this GICM frame.
Component | Frame | Offset | Instance |
---|---|---|---|
GIC Distributor | MSI_base | 0x0004 | GICM_TYPER |
Accesses on this interface are RO.
04/07/2023 11:24; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.